Abstract: Disclosed herein are instrument support systems, as well as related methods, computing devices, and computer-readable media. For example, in some embodiments, an instrument support apparatus may include: first logic to first logic to receive a configuration comprising identifying data related to an instrument that provides telemetry data, and a plurality of settings for the instrument regarding a set of the telemetry data provided by the instrument; second logic to configure a control layer of the instrument to provide the set of the telemetry data according to the plurality of settings; third logic to receive, from the control layer, telemetry data from the set of the telemetry data; fourth logic to format the received telemetry data; and fifth logic to provide the formatted telemetry data for further processing.

Abstract: Systems and methods under the present disclosure can provide communication between instruments or resources at multiple locations. One example is a system of interconnection for various types of assets at multiple laboratories in different locations. Assets, devices, resources, or services at a location can multicast a beacon identifying itself. Verification of the asset, etc., can be done by communicating with a URI associated with that asset. Authentication of assets can be token-based to enable communication. Proxy servers at all or some of the locations can manage authentication and communication between locations and between assets. Tunnels can be implemented between different locations to help ensure secure communication.

Abstract: A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.

Abstract: A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure

Abstract: The invention is a method and apparatus that verifies the design of electronic circuitry containing a function to be tested. An input, such as a random input, is provided to the electronic circuitry containing the function, yielding an output. This output, in turn, is used as input (denominated “inverse input”) to an inverse of the function to be tested. The resulting output (termed “inverse output”) is compared to the original input to the function to be tested to facilitate verification of the design of the circuitry.

Abstract: A method of testing a multi-core processor that includes the steps of receiving a plurality of input signals from a plurality of processor cores (100), and producing an output signal corresponding to a disable state when at least two of the plurality of input signals represent a different logic value (106). A testing device (12) includes a multiplexer (40) responsive to a plurality of input signals (24, 26, 28, 30) from a plurality of processor cores (14, 16, 18, 20), and an output driver (48) responsive to the multiplexer (40). The output driver (48) produces an output signal (62) corresponding to a disable state when at least two of the plurality of input signals (24, 26, 28, 30) represent a different logic value.