Abstract: A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

Abstract: A method and apparatus for testing an electronic device with multiple cores is provided. The method begins when at least one scan is input for scan configuring. A signal having a predetermined number of bits is then input to a decoder. The decoder then outputs at least one assigned test channel based on the output of the decoder. A test control block then switches at least one selected scan in channel to a test control block. A hard macro scan out of channels is then input to a channel maximization device which allocates or re-allocates the channels for testing. Testing proceeds once the channels are allocated. An apparatus includes a programmable scan configuration block for adjusting the number of scan out channels to maximize testing resources and a predetermined bit register in communication with the programmable scan configuration block.

Abstract: A method and apparatus for testing a device memory. The method begins with a generated data and address width from an automatic testing system. The generated data width and the generated address width is compared with the required data width and address width of a device under test and used to set a user bit. If the generated data width and address width match the required data and address width, the user bit is set to zero. If the generated data width and address width do not match the required data width and address width, the user bit is set to 1. The user bit provides address control and data control during testing. The apparatus includes a wireless test access protocol that is electrically connected to a glue logic module. A wireless test access port is electrically connected to the glue logic module as is the device under test.

Abstract: Embodiments contained in the disclosure provide a method of testing an electronic chip. The method comprises: scanning a test program into multiple clock registers; pulsing a clock to activate multiple asynchronous clock domain registers one at a time; staggering capture across and within the multiple asynchronous clock domains; shifting acquired data out of the multiple scan chains simultaneously; and then comparing the data scanned out with the test program data.

Abstract: A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: A through-substrate via (TSV) die includes a substrate with a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface. A plurality of TSVs extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface and include an inner metal core of electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSVs. A tip deformation protecting layer of inorganic dielectric material is on the bottom side surface lateral to the TSV tips. An elastic modulus of the inorganic dielectric material is greater than (>) an elastic modulus of the electrically conductive filler material. A second dielectric layer including a polymer is on the tip deformation protecting layer.

Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.

Abstract: A method of fabricating a semiconductor die includes circuit elements configured to provide a circuit function. A substrate including a bottomside and a topside is provided. At least one multi-layer structure is formed. The forming is done by depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite the first side. The depositing includes flowing a first reactive component and at least a second reactive component. A gas flow ratio of the first reactive component relative to the second reactive component is automatically changed during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from the first side to the second side. A metal layer comprising a second material having a second CTE is formed on the second side. The second CTE is higher than the first CTE.

Abstract: A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

Abstract: An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %.

Abstract: A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150, 160) to form the interconnect line.

Abstract: A system and method for automatically performing validation and/or formatting procedures for a graphical user interface (GUI) described in a markup language file. The GUI markup language description may comprise descriptions of various types of GUI elements for which text is to be validated/formatted, such as form fields, tables, hypertext links, etc. The markup language file may include various custom markup language attributes in order to automatically validate/format text for a GUI element. Validation/formatting procedures for GUI elements may thus be based on custom markup language attributes and are managed by a manager that is automatically instantiated when the application parses the markup language file. This manager interfaces to receive programmatic events that trigger various types of formatting/validating operations to be performed on the GUI elements.

Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150), (160) to form the interconnect line.

Abstract: The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator.

Abstract: The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements of a primary device characteristic from a representative cross-section of a population of devices. The system provides a modeling function, from which is determined a variance for each measurement—forming a corresponding compilation of variances (200). The compilation of variances is evaluated for discontinuities (300), to identify a discontinuity within the compilation of variances. This discontinuity is utilized to determine a demarcation (302) between accurate and inaccurate measurement data.

Abstract: The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements of a primary device characteristic from a representative cross-section of a population of devices. The system provides a modeling function, from which is determined a variance for each measurement—forming a corresponding compilation of variances (200). The compilation of variances is evaluated for discontinuities (300), to identify a discontinuity within the compilation of variances. This discontinuity is utilized to determine a demarcation (302) between accurate and inaccurate measurement data.

Abstract: The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator.