Abstract: An electrostatic discharge (ESD) circuit including a booster cell is disclosed. The ESD circuit may include first and second rails configured to provide power to the ESD circuit. The first rail may include two spaced apart conductors. The ESD circuit may further include an input/output (I/O) pad and a power/ground (P/G) pad. The P/G pad may include a power clamp electrically coupled between the first and second rails. The booster cell may be physically located between the I/O pad and the P/G pad. The booster cell may provide an electrical connection between the two spaced apart conductors.

Abstract: An electrostatic discharge (ESD) circuit including a booster cell is disclosed. The ESD circuit may include first and second rails configured to provide power to the ESD circuit. The first rail may include two spaced apart conductors. The ESD circuit may further include an input/output (I/O) pad and a power/ground (P/G) pad. The P/G pad may include a power clamp electrically coupled between the first and second rails. The booster cell may be physically located between the I/O pad and the P/G pad. The booster cell may provide an electrical connection between the two spaced apart conductors.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.