Patents by Inventor Rajiv Jain

Rajiv Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8312651
    Abstract: Electronic greeting cards include a greeting card with two or more interconnected panels in combination with a digital multimedia player device which includes an electronic display and an audio output, and circuitry which is operative to receive, store and play digital multimedia files and content. The various greeting card structures cover and encapsulate or otherwise house and adorn the digital multimedia player. Digital files are loaded on to the digital multimedia player by a connection to a network, or directly from a data storage device such as an SD card or USB connection or compact flash which interfaces with a port in the digital multimedia player. Pre-recorded digital multimedia greeting card content is either pre-loaded on a portable data storage device, or selected for purchase and downloaded or transferred for replay by the digital multimedia player of the electronic greeting card.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: November 20, 2012
    Assignee: American Greetings Corporation
    Inventors: Josef A. Mandelbaum, Rajiv Jain, Allison Marsh, Kimberly Bikowski, Cathy Tasse, David Mayer, Eliza DeVogel, Katalina Speck, Mary McClain, Sharon Bogdanski, Mindy Leeders, Catherine Gruntman
  • Patent number: 7802386
    Abstract: Electronic greeting cards include a greeting card with two or more interconnected panels in combination with a digital multimedia player device which includes an electronic display and an audio output, and circuitry which is operative to receive, store and play digital multimedia files and content. The various greeting card structures cover and encapsulate or otherwise house and adorn the digital multimedia player. Digital files are loaded on to the digital multimedia player by a connection to a network, or directly from a data storage device such as an SD card or USB connection or compact flash which interfaces with a port in the digital multimedia player. Pre-recorded digital multimedia greeting card content is either pre-loaded on a portable data storage device, or selected for purchase and downloaded or transferred for replay by the digital multimedia player of the electronic greeting card.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: September 28, 2010
    Assignee: American Greetings Corporation
    Inventors: Josef A. Mandelbaum, Rajiv Jain, Allison Marsh, Kimberly Bikowski, Cathy Tasse, David Mayer, Eliza DeVogel, Katalina Speck, Mary McClain, Sharon Bogdanski, Mindy Leeders, Catherine Gruntman
  • Publication number: 20100223824
    Abstract: Electronic greeting cards include a greeting card with two or more interconnected panels in combination with a digital multimedia player device which includes an electronic display and an audio output, and circuitry which is operative to receive, store and play digital multimedia files and content. The various greeting card structures cover and encapsulate or otherwise house and adorn the digital multimedia player. Digital files are loaded on to the digital multimedia player by a connection to a network, or directly from a data storage device such as an SD card or USB connection or compact flash which interfaces with a port in the digital multimedia player. Pre-recorded digital multimedia greeting card content is either pre-loaded on a portable data storage device, or selected for purchase and downloaded or transferred for replay by the digital multimedia player of the electronic greeting card.
    Type: Application
    Filed: May 6, 2010
    Publication date: September 9, 2010
    Inventors: Josef A. Mandelbaum, Rajiv Jain, Allison Marsh, Kimberly Bikowski, Cathy Tasse, David Mayer, Eliza DeVogel, Katalina Speck, Mary McClain, Sharon Bogdanski, Mindy Leeders, Catherine Gruntman
  • Publication number: 20080289230
    Abstract: Electronic greeting cards include a greeting card with two or more interconnected panels in combination with a digital multimedia player device which includes an electronic display and an audio output, and circuitry which is operative to receive, store and play digital multimedia files and content. The various greeting card structures cover and encapsulate or otherwise house and adorn the digital multimedia player. Digital files are loaded on to the digital multimedia player by a connection to a network, or directly from a data storage device such as an SD card or USB connection or compact flash which interfaces with a port in the digital multimedia player. Pre-recorded digital multimedia greeting card content is either pre-loaded on a portable data storage device, or selected for purchase and downloaded or transferred for replay by the digital multimedia player of the electronic greeting card.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Inventors: Josef A. Mandelbaum, Rajiv Jain, Allison Marsh, Kimberly Bikowski, Cathy Tasse, David Mayer, Eliza DeVogel, Katalina Speck, Mary McClain, Sharon Bogdanski, Mindy Leeders, Catherine Gruntman
  • Patent number: 7187228
    Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: March 6, 2007
    Assignee: Quicklogic Corporation
    Inventors: Rajiv Jain, Richard J. Wong
  • Patent number: 7076417
    Abstract: A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: July 11, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Rajiv Jain, Alan Peisheng Su, Chaitali Biswas
  • Patent number: 7031887
    Abstract: A method is provided for exploring alternative architectures for partitioning computer system resources to execute multiple task specifications. An initial master task graph is formed from the multiple task specifications, the initial master task graph including at least one hierarchical task with pointers to either AND sub-task graphs or XOR sub-task graphs. The initial master task graph is processed to provide a selected number of final master task graphs, each of the final master task graphs comprising a list of AND task graphs. A family of architectures is generated for each of the final master task graphs, each of the architectures generated for a given master task graph being capable of executing every AND task graph included therein.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: April 18, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Rajiv Jain, Alan Peisheng Su, Chaitali Biswas
  • Patent number: 6627969
    Abstract: A metal-to-metal conductive plug-type antifuse has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: September 30, 2003
    Assignee: QuickLasic Corporation
    Inventors: Rajiv Jain, Andre Stolmeijer, Mehul D. Shroff
  • Publication number: 20030046044
    Abstract: A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 6, 2003
    Inventors: Rajiv Jain, Alan Peisheng Su, Chaitali Biswas
  • Publication number: 20030028578
    Abstract: A method is provided for exploring alternative architectures for partitioning computer system resources to execute multiple task specifications. An initial master task graph is formed from the multiple task specifications, the initial master task graph including at least one hierarchical task with pointers to either AND sub-task graphs or XOR sub-task graphs. The initial master task graph is processed to provide a selected number of final master task graphs, each of the final master task graphs comprising a list of AND task graphs. A family of architectures is generated for each of the final master task graphs, each of the architectures generated for a given master task graph being capable of executing every AND task graph included therein.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventors: Rajiv Jain, Alan Peisheng Su, Chaitali Biswas
  • Patent number: 6515343
    Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: February 4, 2003
    Assignee: QuickLogic Corporation
    Inventors: Mehul D. Shroff, Rajiv Jain
  • Patent number: 6509209
    Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: January 21, 2003
    Assignee: QuickLogic Corporation
    Inventors: Mehul D. Shroff, Rajiv Jain
  • Patent number: 6378001
    Abstract: A collaborative session is represented by a session object which receives all messages generated by the programs and transmits the messages to all programs participating in the session. The session object can include shared objects which are managed by the session and can be updated without requiring messages to be transmitted over a network. Accordingly, programs may enter a session after it begins and immediately access common session information, such as a state database.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: April 23, 2002
    Assignee: International Business Machines Corp.
    Inventors: Radhakrishna Aditham, Rajiv Jain, Muralidharan Srinivasan
  • Patent number: 6192419
    Abstract: A collaborative application framework is used to build application programs which communicate with a central collaboration manager by means of a predetermined protocol. The predetermined protocol allows converters to be located at the collaboration manager site so that the programs neither include, nor require, preconfigured converters. Accordingly, new programs may easily and inexpensively be added to the system. The framework includes class code information which is incorporated into each application program by subclassing and which allows the program to communicate with the central manager by passing messages. The framework further includes class code for creating in the central manager a session object which receives a first message from a first program, converts the information in the first message into an information format utilized by a second program and forward a second messages to the second program containing information in the appropriate format.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: February 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Radhakrishna Aditham, Rajiv Jain, Muralidharan Srinivasan
  • Patent number: 6169550
    Abstract: A computer method draws overlapped two-dimensional shapes and two-dimensional projections of three-dimensional shapes onto a projection plane in a system of world coordinates X,Y,Z. The method instantiates a plurality of two-dimensional geometry class objects, each of which includes an order attribute specifying an overlapped position for depicting a corresponding two-dimensional shape on a projection plane positioned orthogonally to the Z coordinate of the world coordinate system. The method instantiates a three-dimensional geometry class object including a Z-value for a position along the Z world coordinate of the three-dimensional shape. The method sorts the plurality of two-dimensional geometry class objects by their respective order attributes in a sorting table in the memory. The method sorts the three-dimensional geometry class object by its Z-value in the sorting table and orders it in a composite order with the two-dimensional class objects in the sorting table.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: January 2, 2001
    Assignee: Object Technology Licensing Corporation
    Inventor: Rajiv Jain
  • Patent number: 6154054
    Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: November 28, 2000
    Assignee: QuickLogic Corporation
    Inventors: Mehul D. Shroff, Rajiv Jain, Andre Stolmeijer, Kathryn E. Gordon
  • Patent number: 6151034
    Abstract: A graphics system enables an automatic choice between existing host rendering programs, existing hardware acceleration methods, and enhanced software acceleration programs for rendering graphic primitives. The graphics system accesses the speed and accuracy characterizations of a hardware accelerator attached to the system. Then, for each graphics primitive available from the enhanced software acceleration programs, the graphics system invention compares the speed and accuracy of the attached hardware accelerator with that of the enhanced software acceleration programs. The graphics system invention then selects which graphics primitives should be rendered by the enhanced software acceleration programs and which graphics primitives should be rendered by the attached hardware accelerator.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: November 21, 2000
    Assignee: Object Technology Licensinc Corporation
    Inventors: Rajiv Jain, E. U. Sudhakaran
  • Patent number: 6107165
    Abstract: A metal-to-metal conductive plug-type antifuise has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: August 22, 2000
    Assignee: QuickLogic Corporation
    Inventors: Rajiv Jain, Andre Stolmeijer, Mehul D. Shroff
  • Patent number: 5955751
    Abstract: A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: September 21, 1999
    Assignee: QuickLogic Corporation
    Inventors: Mehul D. Shroff, Rajiv Jain, Andre Stolmeijer, Kathryn E. Gordon
  • Patent number: 5941945
    Abstract: In a colloboration system which allows a plurality of programs to interact, each program registers an "interest" in messages with a session object. The session object, which represents the colloboration session and acts as a collaboration manager, receives all messages but broadcasts a received message only to those programs which have registered an interest in the message. In one embodiment, a colloborative application framework is used to build both the session object and the application programs. The framework includes class code information which is incorporated into each application program by subclassing and which allows each program to communicate with the session object through a predetermined protocol.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: August 24, 1999
    Assignee: International Business Machines Corporation
    Inventors: Radhakrishna Aditham, Rajiv Jain, Muralidharan Srinivasan