Abstract: A method includes populating a template database with templates associated with template identifiers (IDs) identifying the templates. The method also includes generating a data model that references a template within the template database, where the data model includes a template ID referencing the template in the template database, and where the template includes a parameter field. The data model further includes a template parameter to apply to the parameter field and a digital signature for at least the template ID and the template parameter. The method also includes deploying the data model within a distributed ledger.

Abstract: A method of authenticating a passcode entered by a user on an unstable electronic computing device. The method includes receiving an indication that an input is unstable, impacting the ability of a user to provide the input; generating a dynamic keyboard including at least one alphanumeric key, the dynamic keyboard being configured to address the unstable input; presenting the dynamic keyboard to the user; receiving the input from the user, the input comprising a selection of at least one alphanumeric character of a passcode on the dynamic keyboard; and authenticating the input received from the user by comparing the at least one alphanumeric character and a stored passcode.

Abstract: Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host device without halting the execution of the hardware emulator. The software host device can receive the message indicative of the assertion failure event, and execute, asynchronously relative to the execution of the hardware emulator, at least one fail action instruction associated with the assertion failure event.

Abstract: An emulation system comprises a first computing device having a processor configured to generate a synchronization clock signal on receiving a data transfer request. The first computing device further comprises a first non-transitory machine-readable memory buffer storing machine readable binary data. The emulation system further comprises an emulator controller configured to receive the synchronization clock signal from the first computing device. The emulation system further comprises a memory port controller configured to initiate transfer of the machine readable binary data from the first non-transitory machine-readable memory buffer to a non-transitory machine-readable hardware memory, in response to receiving the synchronization clock signal from the emulator controller, during a latency period of the synchronization clock signal.

Abstract: A method for characterizing a microfabrication process and the product thereof is described. A substrate having TSV's formed therein is assessed by determining the geometries and positions of the top and bottom ends of a TSV. Individual TSV's as well as the entire pattern of TSV's formed in a substrate may be assessed.

Abstract: A method for characterizing a microfabrication process and the product thereof is described. A substrate having TSV's formed therein is assessed by determining the geometries and positions of the top and bottom ends of a TSV. Individual TSV's as well as the entire pattern of TSV's formed in a substrate may be assessed.

Abstract: A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method are described. The sense amplifier circuit is described to include: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed alteration circuit having first and second outputs respectively coupled to the first and second inputs via respective first and second capacitors and configured to cause one of the first and second capacitors to discharge to increase the differential voltage when a previously read logic value is opposite the current logic value to be read.

Abstract: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.

Abstract: A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method. In one embodiment, the sense amplifier circuit includes: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed alteration circuit having first and second outputs respectively coupled to the first and second inputs via respective first and second capacitors and configured to cause one of the first and second capacitors to discharge to increase the differential voltage when a previously read logic value is opposite the current logic value to be read.

Abstract: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.

Abstract: A system for inspecting a component, such as a die formed on a silicon wafer, is provided. The system includes a two dimensional inspection system that can locate one or more features, such as bump contacts on the die, and which can also generate feature coordinate data. The system also includes a three dimensional inspection system that is connected to the two dimensional inspection system, such as through an operating system of a processor. The three dimensional inspection system receives the feature coordinate data and generates inspection control data.

Abstract: A system for selecting reference die images, such as for use with a visual die inspection system, is provided. The system includes a die image comparator, which compares a first die image to a second die image in order to create a difference image that contains only the differences between the two die images. The system also includes a difference image analysis system that receives data from the die image comparator. The difference image analysis system analyzes the difference image and determines whether there are any features of the difference image that indicate that either the first die image or the second die image should not be used as a reference die image.

Abstract: A system for selecting reference die images, such as for use with a visual die inspection system, is provided. The system includes a die image comparator, which compares a first die image to a second die image in order to create a difference image that contains only the differences between the two die images. The system also includes a difference image analysis system that receives data from the die image comparator. The difference image analysis system analyzes the difference image and determines whether there are any features of the difference image that indicate that either the first die image or the second die image should not be used as a reference die image.

Abstract: A computer vision apparatus and methods for automatically inspecting 2-dimensional (2D) and 3-dimensional (3D) criteria of objects using a single camera and laser sources. A camera views the object under inspection which is illuminated by a first source of light to highlight the region of interest. This provides image data for 2d analysis by a computer coupled to the system. Subsequently, multiple laser sources mounted on a positioner provide the illumination for collecting images for 3 dimensional analysis. A computer with a monitor is connected to the camera to perform the inspection and analysis and for operator supervision of the system. Specific implementations provided refer to embodiments for inspecting packaged semiconductor devices such as Ball-Grid Arrays (BGAs) packages and Quad Flat Packages (QFPs) packages for package mark inspection, package defect inspection, and solder ball or lead defects.

Abstract: A device (10) identifies a defective object (12) from an image of the object (12) stored as pixel data in a pixel-data memory (52, 54, 56, 58). An inspection-point memory (72, 74, 76, 78) stores inspection-point data for the object (12). The inspection-point data represents inspection points (122, 124, . . . ) that are arranged in circuital (112, 136) and transverse (110) groups, where member inspection points of the circuital groups (112, 136) are also members of different ones of the transverse groups (110). A program memory (84) stores a program, which is executed by a processor (64, 66, 68, 70).

Abstract: A system for transporting and inspecting, seriatim, semiconductor devices with plural prong type or solder ball type leads includes a head for transporting the semiconductor devices from one support structure, such as a tray or tube, to a second support structure, such as a tray or tape, and wherein two dimensional and three dimensional measurements of the positional accuracy of the leads is carried out during the transport process. The inspection apparatus is interposed in the transport path and includes a first optical sensor such as a CCD camera oriented to capture a two dimensional image of the semiconductor device package and compare the image with a predetermined two dimensional image store in a central processing unit (CPU).

Abstract: A lead conditioning system (10) conditions leads (74) of electronic component package (30) and includes a rotary table (16) for holding electronic component package (30) and making accessible the leads (74). A conditioning tool (20) includes conditioner arm (34) and conditioner blade (70) that selectively contacts a predetermined number of the leads (74). A manipulator (22) moves conditioning tool (20) to positions that contact a predetermined number of leads (74) to condition leads (74). A control system (24) controls the operation of manipulator (22).

Abstract: Burr inspection system (120) inspects an electrical lead for a burr (112) in association with the operation of a machine vision lead inspection system (10) and includes machine vision circuitry (50) for forming an image (70) of the electrical lead (72) using machine vision lead inspection system (10). Edge detecting instructions (120) associate with machine vision circuitry (50) for determining a plurality of edges (89, 91) associated with the electrical lead (72). Scan line determining instructions (128) calculate a plurality of scan lines (88, 90) each corresponding to the contour of a selected one of the plurality of edges (89, 91). The scan lines (88, 90) are separated from edges (88, 90) and image (70) by a preselected distance (92). Inspecting circuitry (130) inspects each scan line (88, 90) to detect whether a burr image (112) crosses the scan line (88, 90) to determine the presence of a burr on the electrical lead.

Abstract: The invention is to a system and apparatus for determining the planarity of leads on a semiconductor device. An image system is used to locate the leads with reference to a reference plate on which the device is mounted, and a real-time reference which is used to provide a known correlation between image pixels and linear measurement such as mils.