Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, if a component of the plurality of components is defined in a table and the table includes the condition to be analyzed, acquiring a result for the condition to be analyzed based on table information, and conducting the analysis of the system using the result based on the table information for the component.

Abstract: Selective importance sampling includes: first phase importance sampling of a plurality of data points to form a first subset of data points; determining a center of gravity of the first subset; determining, based upon the center of gravity, an orthogonal hyperplane; and a second phase importance sampling comprising: determining, for each point in the first subset, whether each point is above the hyperplane; and forming a second subset of data points, wherein the second subset is a subset of the first subset and wherein the second subset excludes each point of the first subset that has been determined to be above the hyperplane. The second subset also excludes all points within an ellipse below the hyperplane. Critical radial distances are determined from binary search or projection of first phase samples onto center of gravity direction as well as the maximal radius of the first subset around the center of gravity.

Abstract: A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.

Abstract: A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: Selective importance sampling includes: first phase importance sampling of a plurality of data points to form a first subset of data points; determining a center of gravity of the first subset; determining, based upon the center of gravity, an orthogonal hyperplane; and a second phase importance sampling comprising: determining, for each point in the first subset, whether each point is above the hyperplane; and forming a second subset of data points, wherein the second subset is a subset of the first subset and wherein the second subset excludes each point of the first subset that has been determined to be above the hyperplane. The second subset also excludes all points within an ellipse below the hyperplane. Critical radial distances are determined from binary search or projection of first phase samples onto center of gravity direction as well as the maximal radius of the first subset around the center of gravity.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: In one example, a method for evaluating a system includes obtaining a model of the system that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. In one embodiment, obtaining the model involves constructing a new model; however, in other embodiments, obtaining the model involves accepting or retrieving a pre-constructed model is input. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the model.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.

Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, if a component of the plurality of components is defined in a table and the table includes the condition to be analyzed, acquiring a result for the condition to be analyzed based on table information, and conducting the analysis of the system using the result based on the table information for the component.

Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on table information when a component of the plurality of components is defined in a table and when the table includes the condition to be analyzed, and a module that is configured to conduct the analysis of the circuit using the result based on the table information for the component.

Abstract: In one example, a method for evaluating a system includes constructing a macro-model of the system comprising a multiple-order polynomial equation that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the macro-model.

Abstract: A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.