Patents by Inventor Rajnish K. Prasad

Rajnish K. Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Global timing modeling within a local context
    Patent number: 9384309
    Abstract: Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: July 5, 2016
    Assignee: SYNOPSYS, INC.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez, Rajnish K. Prasad
  • GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT
    Publication number: 20110289464
    Abstract: Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 24, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez, Rajnish K. Prasad