Patents by Inventor Rakesh Chikkanayakanahalli Manjunath

Rakesh Chikkanayakanahalli Manjunath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11469928
    Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ani Xavier, Jagannathan Venkataraman, Nagalinga Swamy Basayya Aremallapur, Aviral Singhal, Arun Mohan, Rakesh Chikkanayakanahalli Manjunath, Aravind Ganesan, Harshavardhan Adepu
  • Publication number: 20220182266
    Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.
    Type: Application
    Filed: June 30, 2021
    Publication date: June 9, 2022
    Inventors: Ani Xavier, Jagannathan Venkataraman, Nagalinga Swamy Basayya Aremallapur, Aviral Singhal, Arun Mohan, Rakesh Chikkanayakanahalli Manjunath, Aravind Ganesan, Harshavardhan Adepu
  • Patent number: 11177986
    Abstract: Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Ganesan, Harshavardhan Adepu, Rakesh Chikkanayakanahalli Manjunath