Abstract: A semiconductor package including i) a first semiconductor die and ii) a second semiconductor die vertically stacked on top of the first semiconductor die. The first semiconductor die includes a first electronic component and a second electronic component, in which the first electronic component operates in accordance with power associated with a first power domain, and the second electronic component operates in accordance with power associated with a second power domain. The second semiconductor die is configured to supply the power associated with the first power domain to the first electronic component of the first semiconductor die, and supply the power associated with the second power domain to the second electronic component of the first semiconductor die.

Abstract: Embodiments of an apparatus are disclosed that may allow for the isolation of power domains. The apparatus may include a first power switch, a second power switch, and a boundary switch. The first power switch may be coupled between a global power supply and a first local power supply, and the second power switch may be coupled between the global power supply and a second local power supply. The first and second power switches may open in response to first and second power down signals respectively. The boundary switch may be coupled between the first local power supply and the second local power supply and may be configured to open in response to an isolation signal.

Abstract: A power estimation tool allows the designer to estimate power usage, at the RTL stage for example, of a high performance electronic system design using available information. This enables power estimation before the circuit schematics are created and early enough for power dissipation to be included in the design optimization. The estimation tool, operable at the RTL level, may provide estimates of power usage of functional blocks and the overall system. The tool can take an HDL description of the proposed design and partition that description into a format which can be analyzed for power usage in an automated fashion. The estimated power use can also be modified to account for different circuit design techniques such domino versus static designs and to account for capacitance and layout considerations. In addition, an empirical estimator for clock and data buffer power usage allows these elements to be accounted for before their design is completed.