Abstract: A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

Abstract: A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the block level. The method includes determining the block layout of an integrated circuit which employs a clock distribution network for distributing clock signals. In addition the method includes providing a mesh distribution network for delivering clock signals to integrated circuit blocks of the integrated circuit. Thereafter, a balanced tree distribution network for delivering clock signals to the components of each block of the integrated circuit is provided. The top level grid provides predictable min/max skew at the top level and the remainder skew budget can be applied to the blocks.

Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Abstract: A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.

Abstract: An apparatus comprising a first memory, a second memory, a control circuit and a flag circuit. The first and second memories may each be configured to store data received from a first data input and present data to a first data output. The control circuit may be configured to control data stored in response to a write clock and control data presented in response to a read clock. The flag circuit may be configured to generate one or more composite flags in response to the first memory and the second memory.

Abstract: An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.