Patents by Inventor Rakshit AGRAWAL

Rakshit AGRAWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616038
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patrick Francis Thompson, Christopher Daniel Manack, Stefan Herzer, Rakshit Agrawal
  • Patent number: 11395408
    Abstract: Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Apple Inc.
    Inventors: Scott D. Morrison, Karthik Shanmugam, Raymundo M. Camenforte, Rakshit Agrawal, Flynn P. Carson, Kiranjit Dhaliwal
  • Publication number: 20220071013
    Abstract: Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: Scott D. Morrison, Karthik Shanmugam, Raymundo M. Camenforte, Rakshit Agrawal, Flynn P. Carson, Kiranjit Dhaliwal
  • Patent number: 10963566
    Abstract: Implementations described herein disclose a malware sequence detection system for detecting presence of malware in a plurality of events. An implementation of the malware sequence detection includes receiving a sequence of a plurality of events, and detecting presence of a sequence of malware commands within the sequence of a plurality of events by dividing the sequence of plurality of events into a plurality of subsequences, performing sequential subsequence learning on one or more of the plurality of subsequences, and generating a probability of one or more of the plurality of subsequences being a malware based on the output of the sequential subsequence.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: March 30, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rakshit Agrawal, Jack Wilson Stokes, III, Karthik Selvaraj, Adrian M. Marinescu
  • Publication number: 20210066229
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 4, 2021
    Inventors: PATRICK FRANCIS THOMPSON, CHRISTOPHER DANIEL MANACK, STEFAN HERZER, RAKSHIT AGRAWAL
  • Patent number: 10938840
    Abstract: Enhanced neural network architectures that enable the determination and employment of association-based or attention-based “interrelatedness” of various portions of the input data are provided. A method of employing an architecture includes receiving a first input data element, a second input element, and a third input element. A first interrelated metric that indicates a degree of interrelatedness between the first input data element and the second input data element is determined. A second interrelated metric is determined. The second interrelated metric indicates a degree of interrelatedness between the first input data element and the third input data element. An interrelated vector is generated based on the first interrelated metric and the second interrelated metric. The neural network is employed to generate an output vector that corresponds to the first input vector and is based on a combination of the first input vector and the interrelated vector.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 2, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jack Wilson Stokes, III, Rakshit Agrawal, Karthik Selvaraj, Adrian M. Marinescu
  • Patent number: 10833036
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patrick Francis Thompson, Christopher Daniel Manack, Stefan Herzer, Rakshit Agrawal
  • Publication number: 20200211992
    Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: PATRICK FRANCIS THOMPSON, CHRISTOPHER DANIEL MANACK, STEFAN HERZER, RAKSHIT AGRAWAL
  • Publication number: 20200120110
    Abstract: Enhanced neural network architectures that enable the determination and employment of association-based or attention-based “interrelatedness” of various portions of the input data are provided. A method of employing an architecture includes receiving a first input data element, a second input element, and a third input element. A first interrelated metric that indicates a degree of interrelatedness between the first input data element and the second input data element is determined. A second interrelated metric is determined. The second interrelated metric indicates a degree of interrelatedness between the first input data element and the third input data element. An interrelated vector is generated based on the first interrelated metric and the second interrelated metric. The neural network is employed to generate an output vector that corresponds to the first input vector and is based on a combination of the first input vector and the interrelated vector.
    Type: Application
    Filed: October 15, 2018
    Publication date: April 16, 2020
    Inventors: Jack Wilson STOKES, III, Rakshit AGRAWAL, Karthik SELVARAJ, Adrian M. MARINESCU
  • Publication number: 20190228154
    Abstract: Implementations described herein disclose a malware sequence detection system for detecting presence of malware in a plurality of events. An implementation of the malware sequence detection includes receiving a sequence of a plurality of events, and detecting presence of a sequence of malware commands within the sequence of a plurality of events by dividing the sequence of plurality of events into a plurality of subsequences, performing sequential subsequence learning on one or more of the plurality of subsequences, and generating a probability of one or more of the plurality of subsequences being a malware based on the output of the sequential subsequence.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Rakshit AGRAWAL, Jack Wilson STOKES, III, Karthik SELVARAJ, Adrian M. MARINESCU