Abstract: A method of manufacturing an integrated circuit includes providing an auxiliary structure between a first section and a second section of a field-effect transistor. A portion of the auxiliary structure is removed, where a gap is formed between the first section and a remaining portion of the auxiliary structure. In the gap, a first insulator structure is provided that separates a first source/drain region formed in the first section and a gate electrode formed between the first and the second section, where the second section may include a second source/drain region.

Abstract: A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a sense amplifier and are connected in each case to a further memory cell. The gates of the further memory cells are driven via a driving circuit device. An equalization voltage of the two bit lines is influenced in the event of a precharge operation, and a capacitive disequilibrium is avoided at inputs of a sense amplifier due to the voltages on the bit lines in the event of reading the memory cell.

Abstract: An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates a cell voltage of the memory cell to be read out and generates a data item with a logical Low or High level depending on the level of the cell voltage at a data terminal. However, if the sense amplifiers are not of identical construction or arrangement, the same cell voltage level is evaluated differently by the first sense amplifier than by the sense amplifier. To match the evaluation performance of the first and second sense amplifiers, the connected bit line pairs are precharged to different precharging voltages before a read access.

Abstract: A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a sense amplifier and are connected in each case to a further memory cell. The gates of the further memory cells are driven via a driving circuit device. An equalization voltage of the two bit lines is influenced in the event of a precharge operation, and a capacitive disequilibrium is avoided at inputs of a sense amplifier due to the voltages on the bit lines in the event of reading the memory cell.

Abstract: An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates a cell voltage of the memory cell to be read out and generates a data item with a logical Low or High level depending on the level of the cell voltage at a data terminal. However, if the sense amplifiers are not of identical construction or arrangement, the same cell voltage level is evaluated differently by the first sense amplifier than by the sense amplifier. To match the evaluation performance of the first and second sense amplifiers, the connected bit line pairs are precharged to different precharging voltages before a read access.