Patents by Inventor Ralf Peter Brederlow
Ralf Peter Brederlow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11581309Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.Type: GrantFiled: February 18, 2022Date of Patent: February 14, 2023Assignee: Texas Instruments IncorporatedInventors: Michael Szelong, James Robert Todd, Tobias Bernhard Fritz, Ralf Peter Brederlow
-
Publication number: 20220173095Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventors: Michael SZELONG, James Robert TODD, Tobias Bernhard FRITZ, Ralf Peter BREDERLOW
-
Patent number: 11257814Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.Type: GrantFiled: May 31, 2019Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Szelong, James Robert Todd, Tobias Bernhard Fritz, Ralf Peter Brederlow
-
Publication number: 20220020915Abstract: In described examples, a circuit includes an analog frontend arranged to generate an analog stress compensating signal in response to a to-be-compensated analog signal and a first-axis stress sensing signal. The analog frontend can comprise a first precision component (e.g., 220) arranged on a piezoelectric material and arranged to generate the to-be-compensated analog signal that is affected by a stress exerted in the piezoelectric material and a directional stress sensor arranged on the piezoelectric material and coupled to the first precision component. The directional stress sensor is arranged to generate the first-axis sensing signal in response to a longitudinal resultant of a stress exerted in the piezoelectric material. A compensating circuit is arranged to generate a compensated output signal in response to the compensating analog signal and to-be-compensated analog signal.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Inventors: Umidjon Nurmetov, Ralf Peter Brederlow, Baher Haroun, Jose Antonio Vieira Formenti, Michael Szelong, Tobias Bernhard Fritz
-
Patent number: 10837845Abstract: Circuitry for determining the direction of incidence of an acoustic signal in an integrated circuit. An electronic circuit includes a packaged integrated circuit. The packaged integrated circuit includes a die. The die includes a plurality of acoustic transducers spaced apart on the die, and a measurement circuit. The plurality of acoustic transducers includes at least a first acoustic transducer and a second acoustic transducer. The measurement circuit is coupled to at least the first acoustic transducer and the second acoustic transducer. The measurement circuit is configured to determine for the first acoustic transducer, a first time at which the first acoustic transducer detects an acoustic signal propagating in the die; and determine for the second acoustic transducer, a second time at which the second acoustic transducer detects the acoustic signal propagating in the die.Type: GrantFiled: December 20, 2018Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ralf Peter Brederlow, Steven Bartling
-
Publication number: 20200227408Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.Type: ApplicationFiled: May 31, 2019Publication date: July 16, 2020Inventors: Michael SZELONG, James Robert TODD, Tobias Bernhard FRITZ, Ralf Peter BREDERLOW
-
Publication number: 20200200618Abstract: Circuitry for determining the direction of incidence of an acoustic signal in an integrated circuit. An electronic circuit includes a packaged integrated circuit. The packaged integrated circuit includes a die. The die includes a plurality of acoustic transducers spaced apart on the die, and a measurement circuit. The plurality of acoustic transducers includes at least a first acoustic transducer and a second acoustic transducer. The measurement circuit is coupled to at least the first acoustic transducer and the second acoustic transducer. The measurement circuit is configured to determine for the first acoustic transducer, a first time at which the first acoustic transducer detects an acoustic signal propagating in the die; and determine for the second acoustic transducer, a second time at which the second acoustic transducer detects the acoustic signal propagating in the die.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Ralf Peter BREDERLOW, Steven BARTLING
-
Patent number: 10547268Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.Type: GrantFiled: December 29, 2017Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tobias Bernhard Fritz, Martin Staebler, Baher Haroun, Peter Fundaro, Jiri Panacek, Ralf Peter Brederlow
-
Patent number: 10352792Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction.Type: GrantFiled: July 14, 2017Date of Patent: July 16, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Umidjon Nurmetov, Ralf Peter Brederlow, Baher Haroun
-
Publication number: 20190207786Abstract: Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.Type: ApplicationFiled: December 30, 2017Publication date: July 4, 2019Inventors: Swaminathan Sankaran, Bradley Allen Kramer, Baher Haroun, Tobias Bernhard Fritz, Ernst Georg Muellner, Ralf Peter Brederlow
-
Patent number: 10320589Abstract: Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.Type: GrantFiled: December 30, 2017Date of Patent: June 11, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Swaminathan Sankaran, Bradley Allen Kramer, Baher Haroun, Tobias Bernhard Fritz, Ernst Georg Muellner, Ralf Peter Brederlow
-
Patent number: 10126792Abstract: A power conversion system includes a maximum load current controller that is operable to limit a load current. For example, in a power conversion system operating in a discontinuous conduction mode (DCM), the maximum load current controller limits the load current by determining an idle period in an active cycle for power switches of the maximum load current controller. The maximum load current controller is optionally operable to approximate values for the time idle period that are substantially equal to theoretically calculated values.Type: GrantFiled: December 1, 2015Date of Patent: November 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Francesco Silvio Santoro, Ralf Peter Brederlow, Neil Gibson, Rüdiger Kuhn
-
Publication number: 20180278195Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.Type: ApplicationFiled: December 29, 2017Publication date: September 27, 2018Inventors: Tobias Bernhard Fritz, Martin Staebler, Baher Haroun, Peter Fundaro, Jiri Panacek, Ralf Peter Brederlow
-
Publication number: 20180231424Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction.Type: ApplicationFiled: July 14, 2017Publication date: August 16, 2018Inventors: Umidjon Nurmetov, Ralf Peter Brederlow, Baher Haroun
-
Publication number: 20170126124Abstract: A power conversion system includes a maximum load current controller that is operable to limit a load current. For example, in a power conversion system operating in a discontinuous conduction mode (DCM), the maximum load current controller limits the load current by determining an idle period in an active cycle for power switches of the maximum load current controller. The maximum load current controller is optionally operable to approximate values for the time idle period that are substantially equal to theoretically calculated values.Type: ApplicationFiled: December 1, 2015Publication date: May 4, 2017Applicant: Texas Instruments Deutschland GmbHInventors: Francesco Silvio Santoro, Ralf Peter Brederlow, Neil Gibson, Rüdiger Kuhn
-
Patent number: 9541989Abstract: A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through the power supply, without additional sensing elements and at extremely low power levels, and to provide such determinations periodically over potentially long periods of time commensurate with the lifetime of a limited power source such as a battery. In a power conversion system operating in a discontinuous conduction mode (DCM), the power transfer estimator determines the charge transferred during each switching cycle, and the total number of switching cycles, to calculate the cumulative amount of power transferred. The power transfer estimator is optionally operable to calculate a value for the inductance to be used in the determination of the cumulative amount of power transferred through the power supply.Type: GrantFiled: November 17, 2014Date of Patent: January 10, 2017Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Francesco Silvio Santoro, Ralf Peter Brederlow, Niel Gibson, Rüdiger Kuhn
-
Publication number: 20160139650Abstract: A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through the power supply, without additional sensing elements and at extremely low power levels, and to provide such determinations periodically over potentially long periods of time commensurate with the lifetime of a limited power source such as a battery. In a power conversion system operating in a discontinuous conduction mode (DCM), the power transfer estimator determines the charge transferred during each switching cycle, and the total number of switching cycles, to calculate the cumulative amount of power transferred. The power transfer estimator is optionally operable to calculate a value for the inductance to be used in the determination of the cumulative amount of power transferred through the power supply.Type: ApplicationFiled: November 17, 2014Publication date: May 19, 2016Inventors: Francesco Silvio Santoro, Ralf Peter Brederlow, Niel Gibson, Rüdiger Kuhn