Patents by Inventor Ralph A. Schweinfurth

Ralph A. Schweinfurth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6191016
    Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Thomas Letson, Patricia Stokley, Peter Charvat, Ralph Schweinfurth
  • Patent number: 5933759
    Abstract: The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: August 3, 1999
    Assignee: Intel Corporation
    Inventors: Phi L. Nguyen, Ralph A. Schweinfurth, Swaminathan Sivakumar
  • Patent number: 5843846
    Abstract: The present invention describes a method for rounding the top corners of a sub-micron trench in a semiconductor device directly after trench formation. In one embodiment of the present invention the etch process uses an etchant made up of a carbon-fluorine gas, an argon gas, and a nitrogen gas. The combination of gases enables the rounding of the top corners of the trench directly after the trench is formed. The combination of the carbon-fluorine and nitrogen gases etch back the silicon nitride and stress relief oxide layers in order to expose the top corners of the trench. As the top corners of the substrate are exposed the nitrogen and argon gases sputter the top corners rounding them as the etch process completes the trench.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: December 1, 1998
    Assignee: Intel Corporation
    Inventors: Phi L. Nguyen, Ralph A. Schweinfurth