Abstract: A data processor (10) has a branch and link address cache (.sup.++ BLAC.sup.++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

Abstract: A data processor (10) has a branch and link address cache ("BLAC") (40) and a BTAC (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

Abstract: A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

Abstract: A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed.