Patents by Inventor Ralph H. Olson

Ralph H. Olson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for executing pipelined three operand construct
    Patent number: 5131086
    Abstract: A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct.
    Type: Grant
    Filed: June 15, 1990
    Date of Patent: July 14, 1992
    Assignee: Edgcore Technology, Inc.
    Inventors: Joseph C. Circello, Richard H. Duerden, Roger W. Luce, Ralph H. Olson
  • Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
    Patent number: 5101341
    Abstract: A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: March 31, 1992
    Assignee: Edgcore Technology, Inc.
    Inventors: Joseph C. Circello, Richard H. Duerden, Roger W. Luce, Ralph H. Olson