Abstract: A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of an antiferroelectric lead-lanthanum-zirconium-titanate. The protective-coating has a thickness of less than ten micrometers (10 ?m) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor.

Abstract: A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of lead-lanthanum-zirconium-titanate (PLZT). The protective-coating has a thickness of less than ten micrometers (10 ?m) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor.

Abstract: A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300° C.

Abstract: A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300° C.

Abstract: A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of lead-lanthanum-zirconium-titanate (PLZT). The protective-coating has a thickness of less than ten micrometers (10 ?m) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor.

Abstract: A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

Abstract: A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

Abstract: A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

Abstract: A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.

Abstract: An electrical assembly that includes an electronic device, a buss bar, and an electrical connection. The electronic device is operable to control electrical energy. The buss bar is configured to distribute electrical energy within the assembly. The electrical connection is configured to electrically interconnect the device and the buss bar. The electrical connection is formed of braided wire. Flat braided wire is advantageous as it is more flexible than a direct connection formed by a sheet-metal type lead frame, and provides for large contact areas capable of carrying higher currents than a wire-to-surface type contact made with a twisted wire that is generally round in shape.

Abstract: A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

Abstract: A multi-layer capacitor includes an anode, a cathode, a dielectric material, a first endcap, and a second endcap. The anode and cathode are formed of one or more layers of interlaced conductive material. The dielectric material is interposed between each of the layers of the anode and the cathode. The first and second endcaps configured to interconnect each of the layers of the anode and cathode, respectively. The endcaps are formed of conductive nano material. A method of forming an endcap of a capacitor configured to interconnect one or more layers of conductive material includes the step of applying conductive nano material to exposed conductive surfaces of at least one of an anode and a cathode of the one or more layers of conductive material. The method also includes the step of exposing the nano material to a source of energy effective to initiate self-sintering of the nano material.

Abstract: An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond.

Abstract: An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond.

Abstract: A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate. The method may also include bending the resulting capacitor into a serpentine arrangement with gaps between the layers that allow venting of evaporated electrode material in the event of a benign failure.

Abstract: A capacitor exhibiting a benign failure mode has a first electrode layer, a first ceramic dielectric layer deposited on a surface of the first electrode, and a second electrode layer disposed on the ceramic dielectric layer, wherein selected areas of the ceramic dielectric layer have additional dielectric material of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer. The added thickness of the dielectric layer in selected areas allows lead connections to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections, whereby the benign failure mode is preserved.

Abstract: A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate.

Abstract: A capacitor exhibiting a benign failure mode has a first electrode layer, a first ceramic dielectric layer deposited on a surface of the first electrode, and a second electrode layer disposed on the ceramic dielectric layer, wherein selected areas of the ceramic dielectric layer have additional dielectric material of sufficient thickness to exhibit a higher dielectric breakdown voltage than the remaining majority of the dielectric layer. The added thickness of the dielectric layer in selected areas allows lead connections to be made at the selected areas of greater dielectric thickness while substantially eliminating a risk of dielectric breakdown and failure at the lead connections, whereby the benign failure mode is preserved.

Abstract: An improved thermal interface material for conducting heat away from an integrated circuit device into a heat sink is a composite material including a metal screen defining openings and a hardened structural bonding agent incorporated into the openings of the metal screen. The improved composite thermal interface material achieves outstanding bonding properties superior to conventional thermal interface materials, while also exhibiting exceptional thermal conductivity.

Abstract: An electronics assembly is provided having a carrier that provides a controlled height variability between electronics packages and a heat sink device. The electronics assembly includes a substrate and electronics packages connected to the substrate. The assembly also includes a heat sink device positioned in thermal communication with a first side of the electronics packages. The assembly further includes a carrier disposed between the substrate and the heat sink device. The carrier has a resilient wall that biases the electronics packages towards the heat sink device such that a controlled bond line is provided between the first side of the electronics packages and the heat sink device.