Abstract: The present invention is a system in which packet-switched (or general purpose network) multimedia data streaming is controlled based on the capabilities of a client and the preferences of a user. A server processor, coupled to the client processor over a packet-switched network, such as the Internet, receives client processor capabilities in association with a request for service for a multimedia type data transfer. The capabilities can be obtained by an application running on the client assessing the capabilities or through prompting of the user. The client capabilities include, for example, processor speed and multimedia encoders of the client. The server can also obtain the preferences of the user of the client processor and respond based on the preferences. Preferences include, for example, the quality of service of the transfer. The capabilities and preferences can be obtained via a query from the server to the client or can be automatically sent with each request.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.

Abstract: Floating point hardware register set is not given to any user level thread unless it is required to perform floating point operations. Thus, for any non-floating thread, its context does not include the floating point hardware state. This effectively reduces the amount of information to be handled when threads are swapped in the processor. During the course of a thread's execution, at the first instance of an attempt by the thread to execute a floating point instruction, the "float-unavailable" exception occurs. This, in turn, invokes the microkernel's floating point exception handler. The function of this exception handler is to make floating point available to the thread that requires it. The exception handler dynamically allocates space for saving the thread's floating point registers, initializes the registers, and turns on the "float-available" bit in its machine state register. Once a thread obtains floating point context, it continues to have it for the remainder of its life.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.

Abstract: In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stage of the pipeline system. Each template is associated with an individual set of data and includes microinstructions for each stage, whether real or virtual, through which the associated set of data passes. The template micromemory store is segmented into a plurality of individually addressable micromemory units with each unit therein storing microinstructions for an individually associated stage in the data processing pipeline system.

Abstract: In a microprogrammed pipelined data processing system, a template family interfacing structure sequences a plurality of templates to the pipelined system for control thereof, each template therein comprising a set of microinstructions for controlling each stage in the pipelined system. The templates are stored in a template micromemory system addressed by an address register and read to a control register. Parameters, grouped into template "Families", of the next template to be used and family parameters of the current template in use are utilized in conjunction to control the initiation of the next template to avoid conflict in any stage in the pipelined system.