Abstract: An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.

Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Abstract: A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

Abstract: In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

Abstract: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.

Abstract: A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.

Abstract: A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.

Abstract: An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.

Abstract: A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.

Abstract: In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

Abstract: A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. Two or more cells in the memory may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.

Abstract: A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage.

Abstract: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

Abstract: A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.

Abstract: A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port.