Patents by Inventor Rama Divakaruni
Rama Divakaruni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20030186502Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: ApplicationFiled: May 27, 2003Publication date: October 2, 2003Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
-
Patent number: 6620676Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: GrantFiled: June 29, 2001Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
-
Patent number: 6605838Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.Type: GrantFiled: September 30, 2002Date of Patent: August 12, 2003Assignees: International Business Machines Corporation, Infineon Technologies North America CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Gerd Fehlauer, Stephan Kudelka, Uwe Schroeder, Helmut H. Tews
-
Publication number: 20030116784Abstract: The invention provides improved DRAM cells using dual gate transistors, DRAM arrays and devices using DRAM cells as well as improved methods for manufacturing such cells, arrays and devices. The DRAM cells of the invention are characterized by the use of a shared bitline contact for each dual gate transistor. The DRAM arrays and devices of the invention are characterized by use of the DRAM cells of the invention and preferably by the use of a relaxed pitch layout for the bitline contacts. The techniques for manufacturing the DRAM arrays and devices of the invention are preferably characterized by use of a relaxed pitch bitline contact configuration which avoids the need for a critical mask.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Applicant: International Business Machines CorporationInventors: Rama Divakaruni, Carl J. Radens
-
Patent number: 6566228Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.Type: GrantFiled: February 26, 2002Date of Patent: May 20, 2003Assignees: International Business Machines Corporation, Infineon TechnologiesInventors: Jochen Beintner, Rama Divakaruni, Jack A. Mandelman, Andreas Knorr
-
Patent number: 6509624Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.Type: GrantFiled: September 29, 2000Date of Patent: January 21, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Carl J. Radens, Wolfgang Bergner, Rama Divakaruni, Larry Nesbit
-
Publication number: 20030003653Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
-
Patent number: 6501131Abstract: The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer.Type: GrantFiled: July 22, 1999Date of Patent: December 31, 2002Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Rama Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman, Rajesh Rengarajan
-
Patent number: 6498061Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.Type: GrantFiled: December 6, 2000Date of Patent: December 24, 2002Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Rama Divakaruni, Stephan Kudelka, Helmut Tews, Irene McStay, Kil-Ho Lee, Uwe Schroeder
-
Patent number: 6472258Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.Type: GrantFiled: November 13, 2000Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin
-
Publication number: 20020149047Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal.Type: ApplicationFiled: April 11, 2001Publication date: October 17, 2002Applicant: INTERNATIONAL BUSINESS MACHINES COPORATIONInventors: Rama Divakaruni, Thomas W. Dyer, Rajeev Malik, Jack A. Mandelman, V.C. Jaiprakash
-
Publication number: 20020140039Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.Type: ApplicationFiled: June 18, 2002Publication date: October 3, 2002Applicant: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin
-
Patent number: 6441423Abstract: The preferred embodiment of the present invention provides an improved capacitor design that overcomes many of the limitations of the prior art. The preferred embodiment of the present invention uses germanium to adjust the work function of the storage node. Specifically, the addition of germanium modifies the fermi level of the storage node, moving the fermi level towards the conduction band. This modification of the fermi level reduces the difference in conduction band-edge potentials between the storage node and the counter electrode, thus reducing the maximum electric potential seen across the capacitor. In the preferred embodiment, p-type doped silicon germanium is formed in the trench capacitor adjacent to the capacitor dielectric layer. A barrier layer is then formed over the doped silicon germanium, and the remaining storage node area is filled with n+-type polysilicon.Type: GrantFiled: May 31, 2000Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni
-
Patent number: 6433397Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.Type: GrantFiled: January 21, 2000Date of Patent: August 13, 2002Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Rama Divakaruni, Louis Lu-Chen Hsu, Yujun Li
-
Patent number: 6429477Abstract: The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimized and performance is improved. Particularly, the formed body contact connects the SOI layer with the underlying substrate to avoid instabilities and leakage resulting from a floating SOI channel region. The formed diffusion contact connects device diffusions to above wiring to facilitate device operation. By providing the body contact and diffusion contact together in a single shared via, the preferred embodiment avoids the area penalty that would result from separate contacts. Additionally, the preferred embodiment provides a body contact that is self aligned with other devices, minimizing tolerances needed while minimizing process complexity.Type: GrantFiled: October 31, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, William R. Tonti
-
Patent number: 6404000Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.Type: GrantFiled: June 22, 2000Date of Patent: June 11, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp., Kabushiki Kaisha ToshibaInventors: Rama Divakaruni, Rajarao Jammy, Byeong Y. Kim, Jack A. Mandelman, Akira Sudo, Dirk Tobben
-
Publication number: 20020068399Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.Type: ApplicationFiled: December 6, 2000Publication date: June 6, 2002Inventors: Rama Divakaruni, Stephan Kudelka, Helmut Tews, Irene McStay, Kil-Ho Lee, Uwe Schroeder
-
Patent number: 6373086Abstract: A deep trench capacitor having a modified sidewall geometry within the collar isolation region such that the threshold voltage of the vertical parasitic MOSFET between a buried-strap out-diffusion and a N+ capacitor plate is significantly increased as compared to a conventional arrangement. By forming a concave notch within the sidewalls of the capacitor, the electrical thickness of the gate dielectric is effectively thicker than its actual physical thickness. Thereby, a reduced amount of gate dielectric and dopant is needed for suppression of vertical parasitic MOSFET conduction.Type: GrantFiled: June 29, 2000Date of Patent: April 16, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Byeong Y. Kim
-
Patent number: 6348394Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.Type: GrantFiled: May 18, 2000Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Herbert Ho, Giuseppe La Rosa, Yujun Li, Jochen Beintner, Radhika Srinivasan
-
Patent number: 6340615Abstract: A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.Type: GrantFiled: December 17, 1999Date of Patent: January 22, 2002Assignee: International Business Machines CorporationInventors: Sundar K. Iyer, Rama Divakaruni, Herbert L. Ho, Subramanian Iyer, Babar A. Khan