Patents by Inventor Ramadas NAMBATYATHU

Ramadas NAMBATYATHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal-insulator-metal capacitor with improved time-dependent dielectric breakdown
    Patent number: 10510825
    Abstract: A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhehui Wang, Hai Cong, Ramadas Nambatyathu
  • METAL-INSULATOR-METAL CAPACITOR WITH IMPROVED TIME-DEPENDENT DIELECTRIC BREAKDOWN
    Publication number: 20190123130
    Abstract: A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 25, 2019
    Inventors: Zhehui WANG, Hai CONG, Ramadas NAMBATYATHU
  • High voltage trench transistor
    Patent number: 9570545
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yemin Dong, Liang Yi, Zhanfeng Liu, Purakh Raj Verma, Ramadas Nambatyathu
  • HIGH VOLTAGE TRENCH TRANSISTOR
    Publication number: 20150236085
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 20, 2015
    Inventors: Yemin DONG, Liang YI, Zhanfeng LIU, Purakh Raj VERMA, Ramadas NAMBATYATHU
  • High voltage trench transistor
    Patent number: 9054133
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yemin Dong, Liang Yi, Zhanfeng Liu, Purakh Raj Verma, Ramadas Nambatyathu
  • HIGH VOLTAGE TRENCH TRANSISTOR
    Publication number: 20130334601
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
    Type: Application
    Filed: July 23, 2013
    Publication date: December 19, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yemin DONG, Liang YI, Zhanfeng LIU, Purakh Raj VERMA, Ramadas NAMBATYATHU