Patents by Inventor Raman Muthukrishnan

Raman Muthukrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7664938
    Abstract: A system including a CPU including logic for executing code from a location and at a time determined by an external entity, a data cache and a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder. The data unit being arbitrarily defined mutually between the data feeder and the CME. The CME being coupled to the CPU. The CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: February 16, 2010
    Assignee: Xambala Corporation
    Inventors: Devendra Tripathi, Sarin Chandran, Raman Muthukrishnan
  • Patent number: 7623524
    Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler incorporates a mechanism to periodically monitor its operating efficiency and perturb its internal state when its efficiency is below a certain desired level.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 24, 2009
    Assignee: Intel Corporation
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Patent number: 7570654
    Abstract: In general, in one aspect, a switching device includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler operates on a pipeline schedule and modifies the requests received to account for grants generated in current period or previous period not reflected in the queues.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Publication number: 20080159145
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a plurality of ingress modules to receive packets from external sources and to store the packets in queues based on flow. A plurality of egress modules transmit packets received from the plurality of ingress modules to external sources. A crossbar matrix provides configurable connectivity between the plurality of ingress modules and the plurality of egress modules. A scheduler receives requests for utilization of the crossbar matrix from at least a subset of the plurality of ingress modules, arbitrates amongst the requests, grants at least a subset of the requests, and configures the crossbar matrix based on the granted requests. The flows are assigned weights defining an amount of data to be transmitted during a period. When a flow meets or exceeds the assigned weight during the period the flow is deactivated from the schedule arbitration.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Patent number: 7324541
    Abstract: In general, in one aspect, a switching device is described that includes a segmentation unit to receive packets and divide packets having a length greater than a maximum segment length into multiple segments. A plurality of queues associated with a source and a destination stores the segments. A request generator generates requests that include external factors including amount of data contained in the queue and at least some subset of priority and age. A scheduler receives the requests and assigns the requests an internal priority based on the external factors. The scheduler processes the requests for the queues by internal priority in order to generate grants. A framer, responsive to the scheduler, aggregates a plurality of segments for the queues that received a grant to form a frame and to transmit the frame to an associated destination. The frame may contain segments associated with different packets.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Publication number: 20050135355
    Abstract: In general, in one aspect, the disclosure describes a switching device that includes a segmentation unit to receive packets and divide packets having a length greater than a maximum segment length into multiple segments. A plurality of queues associated with a source and a destination stores the segments. A request generator generates requests that include external factors including amount of data contained in the queue and at least some subset of priority and age. A scheduler receives the requests and assigns the requests an internal priority based on the external factors. The scheduler processes the requests for the queues by internal priority in order to generate grants. A framer, responsive to the scheduler, aggregates a plurality of segments for the queues that received a grant to form a frame and to transmit the frame to an associated destination. The frame may contain segments associated with different packets.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Publication number: 20050135356
    Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler operates on a pipeline schedule and modifies the requests received to account for grants generated in current period or previous period not reflected in the queues.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Raman Muthukrishnan, Anujan Varma
  • Publication number: 20050135398
    Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler incorporates a mechanism to periodically monitor its operating efficiency and perturb its internal state when its efficiency is below a certain desired level.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Raman Muthukrishnan, Anujan Varma