Abstract: A system and method for providing embedded UPSR protection for SONET networks is described. The STS channels for working and protection rings of a SONET network are input to a SONET overhead processor. The overhead processor comprises a monitor circuit for each standby and working ring. The monitor circuits monitor their respective input STS channels and detect any defined error conditions and/or defined operator commands or anomaly conditions. An unused overhead portion of the input STS channel is dedicated for encoding a binary value representing an error or command condition. In the event of an error or command condition, the highest value is encoded in the dedicated portion of the STS channel. The output from each monitor circuit is input into a comparator circuit of a cross-connect circuit coupled to the overhead processor. The comparator circuit selects the STS channel with the lowest encoded defect or command condition value and outputs this STS channel as data traffic to downstream network devices.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A system and method for providing embedded UPSR protection for SONET networks is described. The STS channels for working and protection rings of a SONET network are input to a SONET overhead processor. The overhead processor comprises a monitor circuit for each standby and working ring. The monitor circuits monitor their respective input STS channels and detect any defined error conditions and/or defined operator commands or anomaly conditions. An unused overhead portion of the input STS channel is dedicated for encoding a binary value representing an error or command condition. In the event of an error or command condition, the highest value is encoded in the dedicated portion of the STS channel. The output from each monitor circuit is input into a comparator circuit of a cross-connect circuit coupled to the overhead processor. The comparator circuit selects the STS channel with the lowest encoded defect or command condition value and outputs this STS channel as data traffic to downstream network devices.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or “bus wrapper”. “Peripheral” virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a “plug and play’ capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.