Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.

Abstract: An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources.

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract: In an embodiment of the present invention, a programmable matrix is provided for flexibly allocating communication resources among functional circuit blocks. For example, in an embodiment of the present invention, a programmable matrix is provided that allocations communications channels such as transceiver channels among various PCIe hard IP blocks that may be contained within a programmable logic device (PLD).

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: An integrated circuit includes a first vertical clock bus and a first interface circuit coupled to provide first global clock signals to the first vertical clock bus. The first interface circuit is coupled to a first external terminal of the integrated circuit. The integrated circuit also includes a second vertical clock bus and a second interface circuit coupled to provide second global clock signals to the second vertical clock bus. The second interface circuit is coupled to a second external terminal of the integrated circuit. A third horizontal clock bus is coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.

Abstract: One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.

Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

Abstract: An integrated circuit with at least two LC-based phase-locked loop circuits and a high-speed serial interface circuit having multiple channels is provided. Each phase-locked loop circuit may include an oscillator having a varactor and multiple inductors. The oscillator may be configured to generate signals at different frequency ranges as determined by the inductors and the varactor. The LC-based phase-locked loop circuits may be produced such that all frequency ranges together provide the continuous coverage of an octave, thereby enabling the phase-locked loop circuits to generate a clock signal with high quality factors and desirable phase noise and jitter performance at an arbitrary frequency. Since the channels of the high-speed serial interface circuit may receive a clock signal having an arbitrary frequency, the high-speed serial interface circuit may be configured to support any communications protocol.