Patents by Inventor Ramanathan Sethuraman

Ramanathan Sethuraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11797343
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Ramanathan Sethuraman, Karthik Kumar, Mark A. Schmisseur, Brinda Ganesh
  • Publication number: 20220222274
    Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 14, 2022
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
  • Publication number: 20220166846
    Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
    Type: Application
    Filed: July 30, 2021
    Publication date: May 26, 2022
    Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
  • Patent number: 11232127
    Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
  • Publication number: 20210373954
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Application
    Filed: August 13, 2021
    Publication date: December 2, 2021
    Inventors: Francesc GUIM BERNAT, Ramanathan SETHURAMAN, Karthik KUMAR, Mark A. SCHMISSEUR, Brinda GANESH
  • Patent number: 11182298
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 23, 2021
    Assignee: INTEL CORPORATION
    Inventor: Ramanathan Sethuraman
  • Patent number: 11093287
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Ramanathan Sethuraman, Karthik Kumar, Mark A. Schmisseur, Brinda Ganesh
  • Patent number: 11082525
    Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
  • Patent number: 11051026
    Abstract: Techniques related to frame re-ordering for video coding are described herein.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Ramanathan Sethuraman, Sumit Mohan, Changliang Wang, Hong Jiang, Jean-Pierre Giacalone
  • Publication number: 20200195520
    Abstract: A function as a service (FAAS) computing system includes processing to adaptively select function flavors to implement requested functions. Processing includes receiving a request to perform a function from an application, discovering one or more flavors for the function, each flavor to implement the function on computing hardware components of computing platforms, and selecting a first function flavor to implement the requested function. Processing further includes causing execution of the first function flavor by a first computing hardware component for the requested function, determining whether performance degradation of the first computing hardware component exists for the first function flavor, and if so, selecting a second function flavor to implement the requested function, and causing execution of the second function flavor by a second computing hardware component for the requested function, and if not, continuing to cause execution of the first function flavor for requests for the function.
    Type: Application
    Filed: April 26, 2019
    Publication date: June 18, 2020
    Inventors: Francesc GUIM BERNAT, Durgesh SRIVASTAVA, Alexander BACHMUTSKY, Ramanathan SETHURAMAN, Harald SERVAT
  • Patent number: 10474219
    Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja
  • Publication number: 20190281132
    Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 12, 2019
    Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
  • Publication number: 20190278631
    Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Francesc GUIM BERNAT, Ramanathan SETHURAMAN, Karthik KUMAR, Mark A. SCHMISSEUR, Brinda GANESH
  • Publication number: 20190243769
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventor: Ramanathan Sethuraman
  • Patent number: 10296464
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Ramanathan Sethuraman
  • Publication number: 20190138534
    Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall
  • Patent number: 10275853
    Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
  • Publication number: 20180165210
    Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventor: Ramanathan Sethuraman
  • Publication number: 20180165200
    Abstract: In one embodiment, a processor includes: a plurality of cores; a plurality of caches associated with the plurality of cores; a dynamic profiler to identify a plurality of instructions having an activity level greater than a threshold level, the dynamic profiler a shared resource of the processor; and a controller to dynamically enable one or more of the plurality of cores to access the dynamic profiler, where the controller is to enable the dynamic profiler to provide hint information regarding the plurality of instructions to a first core of the plurality of cores. Other embodiments are described and claimed.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventor: Ramanathan Sethuraman
  • Publication number: 20170336854
    Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: November 30, 2015
    Publication date: November 23, 2017
    Applicant: Intel Corporation
    Inventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja