Patents by Inventor Ramanathan Sethuraman
Ramanathan Sethuraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11797343Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.Type: GrantFiled: August 13, 2021Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Francesc Guim Bernat, Ramanathan Sethuraman, Karthik Kumar, Mark A. Schmisseur, Brinda Ganesh
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Publication number: 20220222274Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.Type: ApplicationFiled: January 20, 2022Publication date: July 14, 2022Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
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Publication number: 20220166846Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.Type: ApplicationFiled: July 30, 2021Publication date: May 26, 2022Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
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Patent number: 11232127Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.Type: GrantFiled: December 28, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall, Ned Smith
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Publication number: 20210373954Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.Type: ApplicationFiled: August 13, 2021Publication date: December 2, 2021Inventors: Francesc GUIM BERNAT, Ramanathan SETHURAMAN, Karthik KUMAR, Mark A. SCHMISSEUR, Brinda GANESH
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Patent number: 11182298Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.Type: GrantFiled: April 15, 2019Date of Patent: November 23, 2021Assignee: INTEL CORPORATIONInventor: Ramanathan Sethuraman
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Patent number: 11093287Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.Type: GrantFiled: May 24, 2019Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Francesc Guim Bernat, Ramanathan Sethuraman, Karthik Kumar, Mark A. Schmisseur, Brinda Ganesh
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Patent number: 11082525Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.Type: GrantFiled: May 17, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
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Patent number: 11051026Abstract: Techniques related to frame re-ordering for video coding are described herein.Type: GrantFiled: August 31, 2015Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Ramanathan Sethuraman, Sumit Mohan, Changliang Wang, Hong Jiang, Jean-Pierre Giacalone
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Publication number: 20200195520Abstract: A function as a service (FAAS) computing system includes processing to adaptively select function flavors to implement requested functions. Processing includes receiving a request to perform a function from an application, discovering one or more flavors for the function, each flavor to implement the function on computing hardware components of computing platforms, and selecting a first function flavor to implement the requested function. Processing further includes causing execution of the first function flavor by a first computing hardware component for the requested function, determining whether performance degradation of the first computing hardware component exists for the first function flavor, and if so, selecting a second function flavor to implement the requested function, and causing execution of the second function flavor by a second computing hardware component for the requested function, and if not, continuing to cause execution of the first function flavor for requests for the function.Type: ApplicationFiled: April 26, 2019Publication date: June 18, 2020Inventors: Francesc GUIM BERNAT, Durgesh SRIVASTAVA, Alexander BACHMUTSKY, Ramanathan SETHURAMAN, Harald SERVAT
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Patent number: 10474219Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 30, 2015Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja
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Publication number: 20190281132Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.Type: ApplicationFiled: May 17, 2019Publication date: September 12, 2019Inventors: Ramanathan Sethuraman, Timothy Verrall, Ned M. Smith, Thomas Willhalm, Brinda Ganesh, Francesc Guim Bernat, Karthik Kumar, Evan Custodio, Suraj Prabhakaran, Ignacio Astilleros Diez, Nilesh K. Jain, Ravi Iyer, Andrew J. Herdrich, Alexander Vul, Patrick G. Kutch, Kevin Bohan, Trevor Cooper
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Publication number: 20190278631Abstract: Data management for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow a device, such as an endpoint or client device, or another edge resource, to specify criteria for managing data originating from the device and stored in an edge resource, and extends the storage and memory controllers to manage data in accordance with the criteria, including removing stored data that no longer satisfies the criteria. The criteria includes a temporal hint to specify a time after which the data can be removed, a physical hint to specify a list of edge resources outside of which the data can be removed, an event-based hint to specify an event after which the data can be removed, and a quality of service condition to modify the time specified in the temporal hint based on a condition, such as memory and storage capacity of the edge resource in which the data is managed.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Inventors: Francesc GUIM BERNAT, Ramanathan SETHURAMAN, Karthik KUMAR, Mark A. SCHMISSEUR, Brinda GANESH
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Publication number: 20190243769Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.Type: ApplicationFiled: April 15, 2019Publication date: August 8, 2019Inventor: Ramanathan Sethuraman
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Patent number: 10296464Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.Type: GrantFiled: December 9, 2016Date of Patent: May 21, 2019Assignee: Intel CorporationInventor: Ramanathan Sethuraman
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Publication number: 20190138534Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ramanathan Sethuraman, Timothy Verrall
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Patent number: 10275853Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.Type: GrantFiled: April 15, 2015Date of Patent: April 30, 2019Assignee: Intel CorporationInventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
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Publication number: 20180165210Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventor: Ramanathan Sethuraman
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Publication number: 20180165200Abstract: In one embodiment, a processor includes: a plurality of cores; a plurality of caches associated with the plurality of cores; a dynamic profiler to identify a plurality of instructions having an activity level greater than a threshold level, the dynamic profiler a shared resource of the processor; and a controller to dynamically enable one or more of the plurality of cores to access the dynamic profiler, where the controller is to enable the dynamic profiler to provide hint information regarding the plurality of instructions to a first core of the plurality of cores. Other embodiments are described and claimed.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventor: Ramanathan Sethuraman
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Publication number: 20170336854Abstract: Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 30, 2015Publication date: November 23, 2017Applicant: Intel CorporationInventors: Arojit Roychowdhury, Ramanathan Sethuraman, Ajaya V. Durg, Rakesh A. Ughreja