Patents by Inventor Ramaswamy Ranganathan
Ramaswamy Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9208332Abstract: Resource authorization policies and resource scopes may be defined separately, thereby decoupling a set of authorization rules from the scope of resources to which those rules apply. In one example, a resource includes anything that can be used in a computing environment (e.g., a file, a device, etc.). A scope describes a set of resources (e.g., all files in folder X, all files labeled “Y”, etc.). Policies describe what can be done with a resource (e.g., “read-only,” “read/write,” “delete, if requestor is a member of the admin group,” etc.). When scopes and policies have been defined, they may be linked, thereby indicating that the policy applies to any resource within the scope. When a request for the resource is made, the request is evaluated against all policies associated with scopes that contain the resource. If the conditions specified in the policies apply, then the request may be granted.Type: GrantFiled: December 24, 2010Date of Patent: December 8, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Paul Leach, David McPherson, Vishal Agarwal, Mark Fishel Novak, Ming Tang, Ramaswamy Ranganathan, Pranav Kukreja, Andrey Popov, Nir Ben Zvi, Arun K. Nanda
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Patent number: 9045397Abstract: Described herein are high yield methods for making magnolol analogs which are 5,5?-dialkyl-bi-phenyl-2,2?-diols.Type: GrantFiled: December 20, 2011Date of Patent: June 2, 2015Assignee: Colgate-Palmolive CompanyInventors: Ramesh Naik, Sanju Walikar, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
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Patent number: 9000231Abstract: Described herein are high yield methods for making magnolol (5,5?-diallyl-biphenyl-2,2?-diol) and tetrahydro-magnolol (5,5?-dipropyl-biphenyl-2,2?-diol).Type: GrantFiled: June 20, 2011Date of Patent: April 7, 2015Assignee: Colgate-Palmolive CompanyInventors: Ramesh Naik, Sanju Walikar, Ramesh Jayaramaiah, Vangumalla Devaki Devi, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
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Publication number: 20140357902Abstract: Described herein are high yield methods for making magnolol (5,5?-diallyl-biphenyl-2,2?-diol) and tetrahydro-magnolol (5,5?-dipropyl-biphenyl-2,2?-diol).Type: ApplicationFiled: June 20, 2011Publication date: December 4, 2014Applicant: COLGATE-PALMOLIVE COMPANYInventors: Ramesh Naik, Sanju Walikar, Ramesh Jayaramaiah, Vangumalla Devaki Devi, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
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Publication number: 20140343328Abstract: Described herein are high yield methods for making magnolol analogs which are 5,5?-dialkyl-bi-phenyl-2,2?-diols.Type: ApplicationFiled: December 20, 2011Publication date: November 20, 2014Applicant: Colgate-Palmolive CompanyInventors: Ramesh Naik, Sanju Walikar, Govindarajalu Jeyaraman, Koottungalmadhom Ramaswamy Ranganathan
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Patent number: 8813170Abstract: A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.Type: GrantFiled: November 10, 2011Date of Patent: August 19, 2014Assignee: Microsoft CorporationInventors: Mark F. Novak, Paul Leach, Vishal Agarwal, David McPherson, Sunil Gottumukkala, Jignesh Shah, Arun K. Nanda, Nir Ben Zvi, Pranav Kukreja, Ramaswamy Ranganathan
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Publication number: 20130125199Abstract: A policy that governs access to a resource may be tested against real-world access requests before being used to control access to the resource. In one example, access to a resource is governed by a policy, referred to as an effective policy. When the policy is to be modified or replaced, the modification or replacement may become a test policy. When a request is made to access the resource, the request may be evaluated under both the effective policy and the test policy. Whether access is granted is determined under the effective policy, but the decision that would be made under the test policy is noted, and may be logged. If the test policy is determined to behave acceptably when confronted with real-world access requests, then the current effective policy may be replaced with the test policy.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: MICROSOFT CORPORATIONInventors: Mark F. Novak, Paul Leach, Vishal Agarwal, David McPherson, Sunil Gottumukkala, Jignesh Shah, Arun K. Nanda, Nir Ben Zvi, Pranav Kukreja, Ramaswamy Ranganathan
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Patent number: 8283499Abstract: The present invention relates the use of 2,3-dihalonaphthoquinone compounds of Formula I wherein R1 and R2 are leaving groups like halogens selected from the group comprising Cl, Br, I and F and the R1 and R2 may be the same halogen or may contain different halogen groups, or sulphonyl groups, for making napthoquinone compounds of Formula IA wherein X is any aryl, heteroaryl, alkyl, cyclohexyl, substituted cylohexyl groups and the like.Type: GrantFiled: March 6, 2009Date of Patent: October 9, 2012Assignee: Alkem Laboratories LimitedInventors: Sanjay Sukumar Saralya, Shashikumar Hiriyalu Somashekar, Shashiprabha, Shridhara Kanakamajalu, Koottungalmadhom Ramaswamy Ranganathan, Veerasamy Ananthalakshmi, Govindarajalu Jeyaraman, Kothapalli Sundarraja Rao, Kuppuswamy Nagarajan
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Publication number: 20120167158Abstract: Resource authorization policies and resource scopes may be defined separately, thereby decoupling a set of authorization rules from the scope of resources to which those rules apply. In one example, a resource includes anything that can be used in a computing environment (e.g., a file, a device, etc.). A scope describes a set of resources (e.g., all files in folder X, all files labeled “Y”, etc.). Policies describe what can be done with a resource (e.g., “read-only,” “read/write,” “delete, if requestor is a member of the admin group,” etc.). When scopes and policies have been defined, they may be linked, thereby indicating that the policy applies to any resource within the scope. When a request for the resource is made, the request is evaluated against all policies associated with scopes that contain the resource. If the conditions specified in the policies apply, then the request may be granted.Type: ApplicationFiled: December 24, 2010Publication date: June 28, 2012Applicant: MICROSOFT CORPORATIONInventors: Paul Leach, David McPherson, Vishal Agarwal, Mark Fishel Novak, Ming Tang, Ramaswamy Ranganathan, Pranav Kukreja, Andrey Popov, Nir Ben Zvi, Arun K. Nanda
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Patent number: 8163643Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.Type: GrantFiled: May 4, 2010Date of Patent: April 24, 2012Assignee: Linear Technology CorporationInventors: Maurice O. Othieno, Ramaswamy Ranganathan, Frederick E. Beville, David A. Pruitt, William D. Griffitts
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Publication number: 20110004024Abstract: The present invention relates the use of 2,3-dihalonaphthoquinone compounds of Formula I wherein R1 and R2 are leaving groups like halogens selected from the group comprising Cl, Br, I and F and the R1 and R2 may be the same halogen or may contain different halogen groups, or sulphonyl groups, for making napthoquinone compounds of Formula IA wherein X is any aryl, heteroaryl, alkyl, cyclohexyl, substituted cylohexyl groups and the like.Type: ApplicationFiled: March 6, 2009Publication date: January 6, 2011Applicant: ALKEM LABORATORIES LIMITEDInventors: Sanjay Sukumar Saralya, Shashikumar Hiriyalu Somashekar, Shashiprabha, Shridhara Kanakamajalu, Koottungalmadhom Ramaswamy Ranganathan, Veerasamy Ananthalakshmi, Govindarajalu Jeyaraman, Kothapalli Sundarraja Rao, Kuppuswamy Nagarajan
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Patent number: 7531442Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.Type: GrantFiled: November 30, 2005Date of Patent: May 12, 2009Assignee: LSI CorporationInventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
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Publication number: 20070123024Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.Type: ApplicationFiled: November 30, 2005Publication date: May 31, 2007Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
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Patent number: 6998638Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.Type: GrantFiled: May 28, 2004Date of Patent: February 14, 2006Assignee: LSI Logic CorporationInventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
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Patent number: 6991147Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.Type: GrantFiled: August 18, 2003Date of Patent: January 31, 2006Assignee: LSI Logic CorporationInventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
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Patent number: 6963138Abstract: An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.Type: GrantFiled: February 3, 2003Date of Patent: November 8, 2005Assignee: LSI Logic CorporationInventors: Qwai H. Low, Chok J. Chia, Ramaswamy Ranganathan, Tauman T. Lau
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Patent number: 6861748Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.Type: GrantFiled: November 18, 2002Date of Patent: March 1, 2005Assignee: LSI Logic CorporationInventors: Qwai H. Low, Ramaswamy Ranganathan, Rey Torcuato
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Patent number: 6861343Abstract: An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.Type: GrantFiled: October 9, 2002Date of Patent: March 1, 2005Inventors: Chok J. Chia, Qwai H. Low, Ramaswamy Ranganathan
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Patent number: 6825563Abstract: A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer having major orthogonal sides is disposed under the electrically conductive capping layer. The electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction. An electrically conductive second supporting layer having major orthogonal sides is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. The first direction and the second direction are associated one with another by being disposed at a positive value and a negative value of an angle, where the angle is neither zero nor ninety degrees with respect to the major orthogonal sides of the electrically conductive first supporting layer and the electrically conductive second supporting layer.Type: GrantFiled: October 9, 2003Date of Patent: November 30, 2004Assignee: LSI Logic CorporationInventors: Ramaswamy Ranganathan, Maurice Othieno, Qwai H. Low
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Publication number: 20040217487Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.Type: ApplicationFiled: May 28, 2004Publication date: November 4, 2004Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau