Patents by Inventor Ramesh R. Subramanian

Ramesh R. Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11861326
    Abstract: An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote hosts and implemented in memory of the target system. The method further includes updating virtual submission queues for the remote hosts based on the commands stored in the FIFO. The method further includes providing the commands to the NVM subsystem from the FIFO.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 2, 2024
    Assignee: XILINX, INC.
    Inventors: Santosh Singh, Deboleena M. Sakalley, Ramesh R. Subramanian, Pankaj V. Kumbhare, Ravi K. Boddu
  • Patent number: 11388060
    Abstract: An integrated circuit (IC) device includes a network device including a first network port, a second network port, and an internal endpoint port. The IC device further includes a first processing unit including an internal end station. The first processing unit is configured to communicate with the network device using the internal endpoint port. The IC device further includes a second processing unit including a bridge management layer. The second processing unit is configured to communicate with the network device using the internal endpoint port. In various embodiments, the first processing unit and the second processing unit are configured to communicate with each other using a first internal channel.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Ramesh R. Subramanian, Jayaram Pvss, Syed S. Khader
  • Patent number: 11159445
    Abstract: An integrated circuit (IC) device includes a network device. The network device includes first and second network ports each configured to connect to a network, and an internal endpoint port configured to connect to first endpoint having a first processing unit and second endpoint having a second processing unit. A lookup circuit is configured to provide a first forwarding decision for a first frame to be forwarded to the first endpoint. An endpoint extension circuit is configured to determine a first memory channel based on the first forwarding decision for forwarding the first frame, and forward the first frame to the first endpoint using the determined memory channel.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: Xilinx, Inc.
    Inventor: Ramesh R. Subramanian
  • Patent number: 10862802
    Abstract: A network device includes a plurality of ports, a lookup circuit, and a traffic control circuit. The lookup circuit is configured to provide a first action for a first frame to be forwarded using a first forwarding path between a first set of two ports of the plurality of ports. The lookup circuit is further configured to and provide a second action for a second frame to be forwarded using a second forwarding path between a second set of two ports of the plurality of ports. The traffic control circuit configured to forward the first frame based on the first action and forward the second frame based on the second action.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 8, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ramesh R. Subramanian, Ashif Khan Mohammed
  • Patent number: 10853308
    Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ramesh R. Subramanian, Ravinder Sharma, Jayaram Pvss, Michael Zapke, Manjunath Chepuri
  • Patent number: 10541934
    Abstract: A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: January 21, 2020
    Assignee: XILINX, INC .
    Inventors: Ramesh R. Subramanian, Ravinder Sharma, Ashish Banga
  • Patent number: 10511455
    Abstract: A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: XILINX, INC.
    Inventors: Ravinder Sharma, Ramesh R. Subramanian, Ashish Banga
  • Patent number: 10432536
    Abstract: A network device includes a first port, a second port, and a traffic policer circuit. The traffic policer circuit is configured to provide a frame credit and a credit state associated with the frame credit, receive a start of a first frame of a first stream from the first port, and determine a first estimate frame length of the first frame based on the frame credit and credit state. After the first estimate frame length is generated and prior to an end of the first frame is received, the first frame is metered based on the first estimate frame length to mark the first frame with a first marking. After the end of the first frame is received, the frame credit and credit state are updated based on the first frame. The first frame is forwarded to the second port by policing the first frame based on the first marking.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignee: XILINX, INC.
    Inventors: Ramesh R. Subramanian, Ravinder Sharma, Ashif Khan Mohammed
  • Patent number: 10402111
    Abstract: A data storage system includes a bridging device. The bridging device is configured to receive, from a host through a network, a host data block size. A sub-block size is determined based on the host data block size. One or more storage devices are configured to include a plurality of storage sub-blocks each having the sub-block size. A first write command to write first host data including a first number of host data blocks to the one or more storage devices is received. The bridging device compresses the first host data to generate first compressed data, and write the first compressed data to a second number of storage sub-blocks of the one or more storage devices.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventors: Deboleena Sakalley, Ramesh R. Subramanian, Gopikrishna Jandhyala, Santosh Singh, Seong Hwan Kim
  • Patent number: 9934173
    Abstract: An example method of exchanging data between a remote host and a target system includes receiving at least one remote descriptor from the remote host over a front-end fabric at a controller, the at least one remote descriptor specifying a remote buffer in a remote memory of the remote host that is larger than a page size. The method includes adding entries to a table that map the remote buffer to a plurality of page-sized virtual buffers in a virtual address space managed by the controller, generating local descriptors referencing the plurality of paged-sized virtual buffers, receiving a sequence of page-sized direct memory access (DMA) requests at the controller, generating a sequence remote DMA (RDMA) requests from the sequence of DMA requests based on the entries in the table, and sending the sequence of RDMA requests to the remote host over the front-end fabric.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: April 3, 2018
    Assignee: XILINX, INC.
    Inventors: Deboleena Sakalley, Santosh Singh, Ramesh R. Subramanian, Pankaj V. Kumbhare, Ravi K. Boddu
  • Patent number: 8943240
    Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Xilinx, Inc.
    Inventor: Ramesh R. Subramanian