Patents by Inventor Ramesh V. Peri

Ramesh V. Peri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7840845
    Abstract: A method for setting a breakpoint includes the following: receiving an input specifying a location for insertion of a breakpoint in the executable program; determining a breakpoint address for insertion of the breakpoint in the executable program based on the specified location of the breakpoint; writing a breakpoint instruction into a second machine-accessible medium at the breakpoint address; and locking a line containing the breakpoint instruction into the second machine-accessible medium to prevent the breakpoint instruction from being overwritten.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: November 23, 2010
    Assignee: Intel Corporation
    Inventors: Srinivas P. Doddapaneni, Ramesh V. Peri, Gerold P. Mueller, Guido Kehrle
  • Patent number: 7581213
    Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Ramesh V. Peri, Srinivas Doddapaneni
  • Patent number: 7533232
    Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Ramesh V. Peri, John S. Fernando, Ravi Kolagotla, Srinivas P. Doddapaneni
  • Patent number: 6467082
    Abstract: A method for simulating a first processor (e.g., target processor) on a second processor (e.g., host processor) includes translating assembly language instructions associated with the first processor into ‘C’ language code. The ‘C’ language code is then compiled by a compiler program running on the second processor. The compiled code is then executed by the second processor to simulate the first processor. For example, the code may be checked to determine whether it is functionally correct and/or run-time statistics may be collected regarding the program associated with the first processor.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: October 15, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Paul Gerard D'Arcy, Pamela C. Deschler, Sanjay Jinturkar, Kamesh Peri, Ramesh V. Peri, David B. Whalley
  • Patent number: 6253373
    Abstract: The inventive system and method separates the tracking of the loop entry and exit points and loop optimization information, from the generation of the instrumentation code at the loop entry and exit points. Thus, the different phases in the compiler can proceed in an optimal manner with respect to producing the best optimized code. This invention allows the correlation of the source code loops to the object code loops, even though different optimizations are being applied to loops. A loop information database is used to store a history of optimizations about loops, as well as loop entry and exit points, instead of using loop data structures that must be globally maintained. The invention detects the loops in the program code, and assigns a unique identifier to each detected loop. The entry and exit points, as well as the identifier are stored in the database. Any changes to the loops from optimizations are also stored in the database.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: June 26, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Ramesh V. Peri
  • Patent number: 6182208
    Abstract: A system for debugging the computer program present in read-only memory (ROM) contains a debugger, a processor, read-only memory, a bus and a hardware debugging support module. The hardware debugging support module contains a first register called the range start register, a second register called the range end register and a comparator. The debugger uses a list of “n” user specified break points to divide a computer program into “n+1” regions, each of which has a start address and an end address. The first register and the second register of the hardware debugging support module are programmed with the start address and end address of a region which contains a specific address. The comparator is connected to the first register and second register of the hardware debugging support module and is also connected to the bus which connects the read-only memory to the processor.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: January 30, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Ramesh V. Peri, Sanjay Jinturkar, Lincoln Fajardo, Jay Wilshire
  • Patent number: 6088525
    Abstract: The inventive system and method prepares a loop within a section of program code for profiling by placing instrumentation slots into the section at particular points. Entry slots are inserted just prior to the entry point of the loop. If there is a target within the loop of a branch instruction that is located outside of the loop, then the target is changed to point to the first instruction of the entry slots. If there is a fall through within the loop to the entry slots, then a branch instruction is inserted before the first instruction of the entry slots to branch around the entry slots. Exit slots are inserted immediately subsequent to the implicit exit point of the loop, and exit slots are also inserted just prior to the target of the explicit exit instruction. If there is a fall through within the section to the exit slots, then a branch instruction is inserted before a first instruction of the exit slots to branch around the exit slots.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: July 11, 2000
    Assignee: Hewlett-Packard Company
    Inventor: Ramesh V. Peri
  • Patent number: 6079032
    Abstract: A method of analyzing performance of a program executing in a computer system. A user provides a set of user defined region of the program. Thus, a user has the flexibility to choose the regions of program code profiled. The performance of user defined regions of the program is measured by a set of run-time metrics. Each user defined region is associated with a range break point. Run-time metrics measuring the performance of user defined regions of the program are updated, during execution, whenever a range break point is set. The handling of range break points may be implemented, for example, by specialized hardware and software. This method may be less intrusive than instrumentation based profiling but more accurate than sampling based profiling.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: June 20, 2000
    Assignee: Lucent Technologies, Inc.
    Inventor: Ramesh V. Peri