Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.

Abstract: A test system for testing memory modules uses vertically-mounted personal computer (PC) motherboards. Many test adaptor boards that contain test sockets for testing memory modules are mounted horizontally across a test bench. Each test adaptor board connects to a motherboard that tests the memory modules in the test sockets. The motherboard is mounted below and perpendicularly to the test adaptor board. The motherboard is modified to extend the memory bus to edge contact pads along an edge of the motherboard. An edge socket on the test adaptor board mates with the edge contact pads to make electrical connection. A robotic arm inserts a memory module into the test socket, allowing the vertically-mounted motherboard to execute programs to test the memory module. The density of vertically-mounted motherboards is 2-4 times higher than with horizontally-mounted motherboards.

Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: An improvement in a Rambus memory system of the type used in personal computers. On a module level, each RIMM (Rambus Interface Memory Module) includes a positive and a negative module time delay element on the CTM (clock to master) clock line. On a system level, where a motherboard has a plurality of RIMMs coupled to a chipset (i.e. memory controller), a positive or negative system time delay element is placed on the CFM (clock from master line). By virtue of the module and system time delay elements, the clock timing can be adjusted from the data timing, whereby the overall TQ (timing skew between clock and data) can be advantageously reduced to allow more RIMMs to be placed on the same motherboard. What is more, the module and system delays also improve timing margins on the standard Rambus channel so as to increase the robustness of a conventional Rambus system.

Abstract: A test station for testing memory modules uses multiple personal computer (PC) motherboards for performing functional tests on the modules. The motherboards are mounted upside-down with the solder-side up at the desktop level of the test station frame. One or more of the memory-module sockets on each motherboard is removed. A test adaptor board is plugged into the holes of the removed socket, but mounted on the reverse, solder side of the motherboard rather than the component side. The test adaptor board has a test socket that receives a module being tested. An overhead robotic arm picks up memory modules from an input tray and inserts them into test sockets for testing by the motherboards. Since the cables, components, and expansion boards of the motherboards are hidden below the solder-side surface of the motherboards, while the test adaptor board is above, the overhead robotic arm can easily navigate to the test socket without obstruction.

Abstract: Repeater units in a stack are identical. Each repeater unit has an internal repeater and an internal bridge. The repeater stack is dual-speed, with each repeater connecting to a 10 Mbps (10M) backplane bus and to a 100 Mbps (100M) backplane bus in the stack's chassis. The internal repeater has a 10M repeater circuit that connects 10M ports to the 10M bus, and a 100M repeater circuit that connects 100M ports to the 100M bus. Ports are configured for either 10M or 100M operation. Data from 10M ports is repeated to all other 10M ports and to the 10M bus, but not to 100M ports or the 100M bus. Instead, a 10M port is connected to the internal bridge, which is also connected to a 100M port. The internal bridge stores and forwards packets to and from the 10M port and the 100M port. Only one internal bridge in the stack is configured to link the 10M and 100M ports. Other internal bridges are configured to connect a cascading port to the internal repeater. The cascading port is buffered by the internal bridge.

Abstract: A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.

Abstract: Memory modules are tested using a test assembly with a personal computer (PC) motherboard. The motherboard is mounted upside-down with its solder-side up to a metal plate using standoffs. A memory-module socket on the motherboard is removed. An opening is made in the metal plate above the removed socket. A well is attached to the metal plate at the opening. The well supports a test adaptor board below the metal plate so that the test adaptor board has a closer spacing to the motherboard than does the metal plate. The test adaptor board has a test socket that receives a module being tested. Pins from the test adaptor board are plugged into the holes of the removed socket on the motherboard, but mounted on the reverse, solder side of the motherboard rather than the component side. The cables, components, and expansion boards of the motherboards are hidden below the metal plate and motherboard, and can be cooled without cooling the memory module in the test socket.

Abstract: Margin testing of memory modules uses a personal computer (PC) motherboard. A test adaptor board has a test socket that receives a memory module under test. Pins from the test adaptor board are plugged into holes of a removed memory-module socket on the motherboard, mounted on the reverse, solder side of the motherboard. The test adapter board has a voltage regulator that controls the power-supply (Vcc) voltage applied to the module under test. A delay circuit on the test adapter board varies the phase delay of a clock to the memory module under test. Margin control signals are generated by a controller card in the PC's expansion slots, to control Vcc and clock delay to the module under test without changing the motherboard's Vcc voltage. The test program executing on the PC motherboard writes to the controller card to adjust voltage and delay, allowing Vcc and setup and hold margins to be tested.

Abstract: Each stacked repeater has two activity ports that are daisy chained to the activity ports of other repeaters in the stack. Each activity port has an input and an output. The two activity ports connect to the next repeater above and the next repeater below in the stack. Each repeater examines its local network ports to computer stations such as PC's to determine if any are inputting data to the repeater. When any local port is inputting data, the repeater activates both of its activity-port outputs. When no local port is inputting data, the repeater simply passes each activity-port's input through to the other activity-port's output. Thus the activity-port output indicates when either the repeater or an earlier repeater in the chain has a local port inputting data.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A method for a frequency synthesizer with adaptive loop bandwidth is disclosed, which is adjusted by the improved frequency synthesizer includes a phase-locked loop and a phase-locked loop adjustment circuit. The phase-locked loop has loop characteristics including a loop bandwidth, a natural frequency, a damping factor, and the like. The phase-locked loop adjustment circuit is adjusted in response to a change in output frequency.

Abstract: A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks.

Abstract: A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks.

Abstract: A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.

Abstract: A timing recovery scheme disposed to be substantially invariant to the specific composition of an input data sequence. The phase detection network of the present invention will typically be addressed by a data waveform having a plurality of data packets separated by data delimiters. In operation, the phase detection network of the present invention generates a phase error signal in response to the phase difference between a binary data waveform and a periodic clock waveform recovered therefrom. The inventive phase detection network includes a shift register for storing samples of the incident data waveform. The contents of the shift register are monitored by a boundary detection circuit disposed to signal the presence of one of the delimiters within the shift register. Upon detection of such a delimiter a boundary correction circuit is disposed to generate a phase detection enable signal.

Abstract: A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal.

Abstract: An improved circuit topology for implementing level detection and data restoration operations on an input sinusoid. The differential high-frequency level detector and data restoration circuits of the present invention each include a differential input having a pair of circuit nodes for receiving a differential input signal. A slicing offset network is disposed to generate first and second differential signals in response to the differential input signal. The present invention further includes first and second comparators for respectively providing latch set and latch reset signals in response to the first and second offset differential signals. The data restoration circuit of the present invention further includes a latch operative to synthesize a recovered data waveform in accordance with pairs of set and reset signals. Similarly, the inventive level detector includes a latch which utilizes set and reset signals to generate a level detection signal.