Patents by Inventor Ramprasad Satagopan
Ramprasad Satagopan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7003639Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: GrantFiled: June 21, 2004Date of Patent: February 21, 2006Assignee: Rambus Inc.Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Publication number: 20040230739Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: ApplicationFiled: June 21, 2004Publication date: November 18, 2004Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Patent number: 6782460Abstract: A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.Type: GrantFiled: May 27, 2003Date of Patent: August 24, 2004Assignee: Rambus Inc.Inventors: Ramprasad Satagopan, Richard M. Barth
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Publication number: 20040139293Abstract: A system and method for controlling data access in a memory system is disclosed. The memory system is characterized by the use of a transport and retire write request, memory devices incorporating a retire buffer, and inherent data retirement. Addresses associated with un-retired write data are stored in the memory controller and compared to the address of a read request following one or more write requests. Where a read request is directed to an address associated with an un-retired write data, the read request is stalled in the memory controller.Type: ApplicationFiled: October 27, 2003Publication date: July 15, 2004Applicant: Rambus Inc.Inventors: Richard M. Barth, Ramprasad Satagopan, Anil V. Godbole
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Patent number: 6754783Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: GrantFiled: February 18, 2003Date of Patent: June 22, 2004Assignee: Rambus Inc.Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Patent number: 6640292Abstract: A system and method for controlling data access in a memory system is disclosed. The memory system is characterized by the use of a transport and retire write request, memory devices incorporating a retire buffer, and inherent data retirement. Addresses associated with un-retired write data are stored in the memory controller and compared to the address of a read request following one or more write requests. Where a read request is directed to an address associated with an un-retired write data, the read request is stalled in the memory controller.Type: GrantFiled: September 10, 1999Date of Patent: October 28, 2003Assignee: Rambus Inc.Inventors: Richard M. Barth, Ramprasad Satagopan, Anil V. Godbole
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Publication number: 20030196059Abstract: A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.Type: ApplicationFiled: May 27, 2003Publication date: October 16, 2003Applicant: Rambus Inc.Inventors: Ramprasad Satagopan, Richard M. Barth
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Publication number: 20030159004Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: ApplicationFiled: February 18, 2003Publication date: August 21, 2003Applicant: Rambus, Inc.Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Patent number: 6571325Abstract: A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory system.Type: GrantFiled: September 23, 1999Date of Patent: May 27, 2003Assignee: Rambus Inc.Inventors: Ramprasad Satagopan, Richard M. Barth
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Patent number: 6523089Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: GrantFiled: July 16, 2001Date of Patent: February 18, 2003Assignee: Rambus Inc.Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Patent number: 6453401Abstract: A memory controller includes a constraint tracking and checking unit for tracking and checking timing constraints imposed by respective issued commands to access a memory. A constraint tracking subunit includes multiple tracking circuits and an allocation circuit. The allocation circuit is configured to allocate a selected tracking circuit from among the multiple tracking circuits each time that a specific command is issued. The allocated tracking circuit is configured to track the timing constraint imposed by the specific command. A constraint checking subunit is configured to determine if the tracked timing constraint is pending against issuance of a generated command to access the memory and to generate a blocking signal when a timing constraint is pending against issuance of a generated command.Type: GrantFiled: July 2, 1999Date of Patent: September 17, 2002Assignee: Rambus Inc.Inventors: Richard M. Barth, Ramprasad Satagopan, Anil V. Godbole
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Patent number: 6373768Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.Type: GrantFiled: September 23, 1999Date of Patent: April 16, 2002Assignee: Rambus IncInventors: Steven C. Woo, Ramprasad Satagopan, Richard M. Barth, Ely K. Tsern, Craig E. Hampel
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Publication number: 20020040416Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.Type: ApplicationFiled: July 16, 2001Publication date: April 4, 2002Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
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Patent number: 6310814Abstract: An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.Type: GrantFiled: August 8, 2000Date of Patent: October 30, 2001Assignee: Rambus, Inc.Inventors: Craig E. Hampel, Richard M. Barth, Paul G. Davis, Bradley A. May, Ramprasad Satagopan, Frederick A. Ware
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Publication number: 20010014049Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.Type: ApplicationFiled: September 23, 1999Publication date: August 16, 2001Inventors: STEVEN C. WOO, RAMPRASAD SATAGOPAN, RICHARD M. BARTH, ELY K. TSERN, CRAIG E. HAMPEL
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Patent number: 6195733Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.Type: GrantFiled: October 21, 1998Date of Patent: February 27, 2001Assignee: Intel CorporationInventors: N. Gopalan Nair, David Regenold, Parviz Hatami, Ramprasad Satagopan
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Patent number: 6021076Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.Type: GrantFiled: July 16, 1998Date of Patent: February 1, 2000Assignee: Rambus IncInventors: Steven C. Woo, Ramprasad Satagopan, Richard M. Barth, Ely K. Tsern, Craig E. Hampel
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Patent number: 5909702Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.Type: GrantFiled: September 30, 1996Date of Patent: June 1, 1999Assignee: Intel CorporationInventors: Marc Jalfon, David Regenold, Franco Ricci, Ramprasad Satagopan
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Patent number: 5890013Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.Type: GrantFiled: September 30, 1996Date of Patent: March 30, 1999Assignee: Intel CorporationInventors: N. Gopalan Nair, David Regenold, Parviz Hatami, Ramprasad Satagopan
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Patent number: 5513346Abstract: An interrupt processor controller (IPC) through which all interprocessor interrupts are routed in a complex integrated circuit. For processors which receive external interrupts, the interrupt processor controller may receive those interrupts and route those as well to the particular processor. The IPC includes interrupt routing logic which determines when a subsequent interrupt will cause an error condition with a previously instigated interrupt that has not been cleared. When such a condition occurs, a bit is set in an error detect register that is coupled to the interrupt routing logic. All of the bits of the error detect register are logically OR'ed, the output of which is routed to a single dedicated pin for indicating an interrupt error condition has occurred. This pin may have its signal routed back into the complex integrated circuit for signaling a trap handler or some other mechanism that an interrupt error condition has occurred.Type: GrantFiled: October 21, 1993Date of Patent: April 30, 1996Assignee: Intel CorporationInventors: Ramprasad Satagopan, David R. Regenold