Abstract: Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.