Abstract: Embodiments of the invention may provide a phase locked loop (PLL) for a long-range and short-range frequency-modulated carrier-frequency (FMCW) RADAR system, including: a single feedback loop for generating a control signal based on differences between an output signal of the RADAR and a reference signal; a first voltage-controlled oscillator (VCO) adapted to generate a first output signal having a first loop bandwidth using the control signal; a second VCO adapted to generate a second output signal having a second loop bandwidth using the control signal; and an output switch for selecting one of the first output signal and the second output signal and outputting the selected signal as the output signal of the RADAR.

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.