Abstract: A non-volatile memory cell includes heavily doped source 12 and drain 14 regions separated by a channel region 16. The source 12 and drain 14 are isolated from floating gate 18 and control gate 22 by thick oxide 36. A floating gate 18 is formed over and insulated from a portion of said channel region 16 adjacent to the source 12 and a control gate 22 is formed over and insulated from the floating gate 18 and the remaining portion of the channel region 16. The cell is programmed by applying a nearly reference voltage V.sub.s to the source region 12 and applying a drain voltage V.sub.D to the drain region 14. A gate voltage V.sub.G is applied to the control gate 22 such that an inversion region 15 is formed in the remaining portion of said channel region 16 such that the floating gate 18 is charged up by hot electron injection on the side away from the source junction. The source junction is self aligned to floating gate and is graded for efficient erase. Other key features and methods are also disclosed.