Abstract: Removeable couplings are provided for connecting a memory module to a host processor of an IHS (Information Handling System). The coupling includes electrical contacts and fasteners for positioning the electrical contacts within an empty memory slot of the IHS motherboard. The housing extends between two ends of the coupling and receives the memory module when the memory module is installed in the IHS. The positioned electrical contacts are then seated within the memory slot of the motherboard by the downward force applied by an administrator in installing the memory module to the coupling. The force applied in installing the memory module also serves to connect the electrical contacts of the coupling to a memory channel of the motherboard. The removeable coupling is not attached to the motherboard when the memory module is not installed in the IHS, thus eliminating signal stubs in the memory channel.

Abstract: Removeable couplings are provided for connecting a memory module to a host processor of an IHS (Information Handling System). The coupling includes electrical contacts and fasteners for positioning the electrical contacts within an empty memory slot of the IHS motherboard. The housing extends between two ends of the coupling and receives the memory module when the memory module is installed in the IHS. The positioned electrical contacts are then seated within the memory slot of the motherboard by the downward force applied by an administrator in installing the memory module to the coupling. The force applied in installing the memory module also serves to connect the electrical contacts of the coupling to a memory channel of the motherboard. The removeable coupling is not attached to the motherboard when the memory module is not installed in the IHS, thus eliminating signal stubs in the memory channel.

Abstract: In some examples, a logic device may be connected to: (i) a ThunderBolt (TBT) output of a CPU that lacks a DisplayPort (DP) input and (ii) a DP output of a GPU. The logic device may determine a presence of a video signal, e.g., either: (1) TBT video from the CPU or (2) DP video from the GPU. The logic device may re-time the video signal to create re-timed video and output the re-timed video using a USB-C port. If the logic device determines that the video signal is DP, then the logic device may select a DisplayPort Alternate Mode of the USB-C port and output the re-timed video signal using four differential pairs of the USB-C port. If the logic device determines that the video signal is TBT, then the logic device may output the re-timed video signal using two differential pairs of the USB-C port.

Abstract: A feedback line to an embedded controller from a component that intermittently sends data not distinguishable by the embedded controller initiates an error if data expected at the embedded controller is not distinguishable, such as with low cooling fan speed tachometer feedback. The embedded controller has a resistor divider circuit associated with the component that provides a high or low pin value at the embedded circuit based upon whether a component interfaces with a pin, such as a pulse width modulation output. The embedded controller checks for presence of the component in the absence of feedback as a reference to know whether an error exists relating to component feedback.

Abstract: A feedback line to an embedded controller from a component that intermittently sends data not distinguishable by the embedded controller initiates an error if data expected at the embedded controller is not distinguishable, such as with low cooling fan speed tachometer feedback. The embedded controller has a resistor divider circuit associated with the component that provides a high or low pin value at the embedded circuit based upon whether a component interfaces with a pin, such as a pulse width modulation output. The embedded controller checks for presence of the component in the absence of feedback as a reference to know whether an error exists relating to component feedback.

Abstract: Adapters, systems and methods are provided that may be implemented to adapt a Peripheral Component Interconnect Express (PCIe) expansion (or add-in) card for mounting into a PCIe component bay (e.g., front-accessible “flex bay”) of an information handling system chassis, such as desktop, server or tower computer chassis. An adapter may be provided that carries an edge mount PCIe expansion card that may be mechanically inserted (e.g., in place of a solid state drive “SSD” carrier or other PCIe peripheral component carrier) into the bay to electrically interface the PCIe expansion card with PCIe lane/s and other signal pins of a blind mate PCIe interface bay connector that extends outwardly into a component bay from the distal side (or rear) of the bay.

Abstract: Sleep modes use non-volatile dual inline memory modules (NVDIMMs) to reduce electrical power and execution times. An S3 suspend-to-RAM, for example, may store a system state to NVDIMM via a high-speed memory bus. Likewise, an S4 suspend-to-disk may store a restoration file to the NVDIMM via the high-speed memory bus. When a server or other information handling system is then awakened, execution resumes in less time due to the NVDIMM.

Abstract: A system, method, and computer-readable medium are disclosed for supporting wireless security access via a multi-function information handling system bay. In certain embodiments, the wireless security access is provided via a security access device configured to fit within the multi-function information handling system. In certain embodiments, the security access device includes a narrow antenna with one full length side in conjunction with high gain and an alignment bar for best matching provides the security access device with the ability to include a near field communications (NFC) type transmitter within the security access device.

Abstract: Adapters, systems and methods are provided that may be implemented to adapt a Peripheral Component Interconnect Express (PCIe) expansion (or add-in) card for mounting into a PCIe component bay (e.g., front-accessible “flex bay”) of an information handling system chassis, such as desktop, server or tower computer chassis. An adapter may be provided that carries an edge mount PCIe expansion card that may be mechanically inserted(e.g., in place of a solid state drive “SSD” carrier or other PCIe peripheral component carrier) into the bay to electrically interface the PCIe expansion card with PCIe lane/s and other signal pins of a blind mate PCIe interface bay connector that extends outwardly into a component bay from the distal side (or rear) of the bay.

Abstract: Sleep modes use non-volatile dual inline memory modules (NVDIMMs) to reduce electrical power and execution times. An S3 suspend-to-RAM, for example, may store a system state to NVDIMM via a high-speed memory bus. Likewise, an S4 suspend-to-disk may store a restoration file to the NVDIMM via the high-speed memory bus. When a server or other information handling system is then awakened, execution resumes in less time due to the NVDIMM.

Abstract: A system, method, and computer-readable medium are disclosed for supporting wireless security access via a multi-function information handling system bay. In certain embodiments, the wireless security access is provided via a security access device configured to fit within the multi-function information handling system. In certain embodiments, the security access device includes a narrow antenna with one full length side in conjunction with high gain and an alignment bar for best matching provides the security access device with the ability to include a near field communications (NFC) type transmitter within the security access device.

Abstract: A display provides power to an information handling system through a display cable. The display cable includes a power wire and an auxiliary channel. The display and information handling system communicate through the auxiliary channel to coordinate power transfer from the display to the information handling system, such as in the form of a trickle charge to a battery integrated in the information handling system.

Abstract: A secondary graphics processor control system includes a secondary graphics processor. A controller is coupled to the secondary graphics processor. The controller detects the start of an application that is associated with a secondary graphics processor and then determines a power capability of a battery. The controller then either prevents enablement of the secondary graphics processor if the power capability is below a predetermined threshold such that only a primary graphics processor processes graphics for the application, or allows enablement of the secondary graphics processor if the power capability is above the predetermined threshold such that the secondary graphics processor processing graphics for the application. The primary graphics processor may be an integrated graphics processing unit (iGPU) provided by a system processor that is mounted to a board, and the secondary graphics processor may be a discrete graphics processing unit (dGPU) that is coupled to the board.

Abstract: A display provides power to an information handling system through a display cable. The display cable includes a power wire and an auxiliary channel. The display and information handling system communicate through the auxiliary channel to coordinate power transfer from the display to the information handling system, such as in the form of a trickle charge to a battery integrated in the information handling system.

Abstract: A display provides power to an information handling system through a display cable. The display cable includes a power wire and an auxiliary channel. The display and information handling system communicate through the auxiliary channel to coordinate power transfer from the display to the information handling system, such as in the form of a trickle charge to a battery integrated in the information handling system.

Abstract: An information handling system includes a video selector to convert a first video signal into a second video signal, convert the first video signal into a third video signal, and couple a video output to a selected one of a first video input or a second video input.

Abstract: A secondary graphics processor control system includes a secondary graphics processor. A controller is coupled to the secondary graphics processor. The controller detects the start of an application that is associated with a secondary graphics processor and then determines a power capability of a battery. The controller then either prevents enablement of the secondary graphics processor if the power capability is below a predetermined threshold such that only a primary graphics processor processes graphics for the application, or allows enablement of the secondary graphics processor if the power capability is above the predetermined threshold such that the secondary graphics processor processing graphics for the application. The primary graphics processor may be an integrated graphics processing unit (iGPU) provided by a system processor that is mounted to a board, and the secondary graphics processor may be a discrete graphics processing unit (dGPU) that is coupled to the board.

Abstract: An information handling system includes a video selector to convert a first video signal into a second video signal, convert the first video signal into a third video signal, and couple a video output to a selected one of a first video input or a second video input.

Abstract: An information handling system includes a video processor that provides a first video signal in a first video format; a display that receives a second video signal in a second video format; and another display that receives a third video signal in a third video format. The first, second, and third video formats are all different from each other. The information handling system also includes a mid-stream frame buffer that stores video information from the first, second, and third video signals, and a video selector coupled to the mid-stream frame buffer the video processor and the displays. The video selector converts the First video signal into the second and third video signals and couples the video processor to a selected display.

Abstract: An improved system and method for selectively applying LCD Response Time Compensation (LRTC) to areas of an LCD panel containing video motion. Motion vectors contained within macroblocks in a compressed video stream are utilized to qualify whether individual pixels in a video frame are a candidate for LRTC. In various embodiments of the invention, computationally expensive LRTC can be selectively applied, pixel-by-pixel, which can result in portable information system power savings by reducing the number of computational cycles and the amount of graphics controller power overhead.