Abstract: A virtual input queue 80 count frames of data arriving an input port zo in an Ethernet switch 10 using shared memory 50. The shared memory 50 is allocated among 1-N input ports based on either a static or dynamic memory scheme. The static scheme allocates the shared memory 50 evenly among the input ports 20 or based on the input port transmission rate. In the dynamic memory scheme, the range of a virtual input queue's occupancy is divided into an underload zone, a normal load zone and an overload zone. When the virtual input queue is in the underload zone, the input port is kept on and reserved a memory capacity equal to a low threshold. When a virtual input queue is in the normal load zone, the virtual on queue 80 is reserved an additional amount of memory and the link is kept on or is turned on whenever possible. The memory capacity not used or reserved by any input port operating in at least the underload zone and normal load zone is shared by the input ports operating in the overload zone.

Abstract: A programmable fast packet switch testbed (10) for use in the evaluation of prototype architectures and traffic management algorithms is disclosed. The programmable switch (10) is arranged as an add-on peripheral to a conventional computer system including a host central processing unit (CPU) (2). The switch (10) includes a plurality of port processors (14) in communication with port interfaces (12); each of the port interfaces (12) is a conventional interface for high data rate communication, while the port processors (14) are programmable logic devices. The switch fabric is realized in a multiple slice fashion, by multiple programmable logic devices (18). A central arbiter (30), also realized in programmable logic, controls routing of cells within the switch (10).

Abstract: A packet switch (26) has N digital input ports (28) each of bandwidth B for receiving data cells including destination addresses for determining output ports, a shared input cache (32), N memory modules (36) of bandwidth N.times.B for buffering, a switch fabric (38), and N digital output ports (40). A digital multiplexer (30) receives each data cell from the input ports (28) and writes it to the shared input cache (32) together with a corresponding port queue number, queue position, and memory module number in response to its destination address so that (1) cells having the same queue number are cyclically assigned to different memory modules (36) and (2) cells having the same queue position are cyclically assigned to different memory modules (36). A digital demultiplexer (34) reads each data cell from the shared input cache (32) and writes it to one of the N memory modules (36) according to its assigned memory module number and queue position.