Patents by Inventor Randall L. Case

Randall L. Case has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080210974
    Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P?doped layers have a combined thickness of about 5 ?m to about 12 ?m.
    Type: Application
    Filed: January 11, 2008
    Publication date: September 4, 2008
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Jifa Hao, John L. Benjamin, Randall L. Case, Joe L. Yun
  • Patent number: 7332750
    Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P? doped layers have a combined thickness of about 5 ?m to about 12 ?m.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: February 19, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jifa Hao, John L. Benjamin, Randall L. Case, Jae J. Yun
  • Patent number: 6358825
    Abstract: In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about 800° C., and the platinum is diffused into the substrate as its temperature is increased at a rate of about 5° C./minute to a first selected temperature of about 850-950° C. Platinum diffusion is continued while the substrate is maintained at the first selected temperature for about 30-60 minutes. The substrate temperature is then increased at a rate of about 5° C./minute to a second selected temperature above 950° C. to about 1000° C., and the substrate is maintained at the second selected temperature for about 5-30 minutes before cooling.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: March 19, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jifa Hao, Randall L. Case, John L. Benjamin