Patents by Inventor Randy J. Aksamit
Randy J. Aksamit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10217732Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.Type: GrantFiled: June 25, 2014Date of Patent: February 26, 2019Assignee: INTEL CORPORATIONInventors: Rany T. Elsayed, Niti Goel, Silvio E. Bou-Ghazale, Randy J. Aksamit
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Patent number: 9720484Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.Type: GrantFiled: March 23, 2015Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Ming Zhang, Chris Wilkerson, Greg Taylor, Randy J. Aksamit, James Tschanz
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Publication number: 20170018543Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.Type: ApplicationFiled: June 25, 2014Publication date: January 19, 2017Applicant: INTEL CORPORATIONInventors: Rany T. ELSAYED, Niti GOEL, Silvio E. BOU-GHAZALE, Randy J. AKSAMIT
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Publication number: 20150192977Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventors: Ming ZHANG, Chris WILKERSON, Greg TAYLOR, Randy J. AKSAMIT, James TSCHANZ
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Patent number: 9015507Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.Type: GrantFiled: September 26, 2013Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: Ming Zhang, Chris Wilkerson, Greg Taylor, Randy J. Aksamit, James Tschanz
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Publication number: 20140032827Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Inventors: Ming Zhang, Chris Wilkerson, Greg Taylor, Randy J. Aksamit, James Tschanz
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Patent number: 8589706Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.Type: GrantFiled: December 26, 2007Date of Patent: November 19, 2013Assignee: Intel CorporationInventors: Ming Zhang, Chris Wilkerson, Greg Taylor, Randy J. Aksamit, James Tschanz
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Patent number: 7626434Abstract: In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.Type: GrantFiled: March 30, 2007Date of Patent: December 1, 2009Assignee: Intel CorporationInventor: Randy J. Aksamit
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Patent number: 7492201Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.Type: GrantFiled: August 27, 2007Date of Patent: February 17, 2009Assignee: Marvell International Ltd.Inventor: Randy J. Aksamit
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Publication number: 20080238510Abstract: In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventor: Randy J. Aksamit
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Patent number: 7262648Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.Type: GrantFiled: August 3, 2004Date of Patent: August 28, 2007Assignee: Marvell International Ltd.Inventor: Randy J. Aksamit
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Patent number: 7170327Abstract: In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the data-retention inverters from a supplemental voltage supply through a well tap during a standby mode. The supply-switching subcircuit switches from a regular voltage supply to the supplemental voltage supply in response to the sleep signal.Type: GrantFiled: June 27, 2003Date of Patent: January 30, 2007Assignee: Intel CorporationInventor: Randy J. Aksamit
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Publication number: 20040266092Abstract: In embodiments, a data-retention circuitry comprises data-retention inverters in a feedback loop, an isolation subcircuit to isolate the inverters from a pass-gate subcircuit in response to a sleep signal, and a supply-switching subcircuit to provide current to the data-retention inverters from a supplemental voltage supply through a well tap during a standby mode. The supply-switching subcircuit switches from a regular voltage supply to the supplemental voltage supply in response to the sleep signal.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Applicant: Intel CorporationInventor: Randy J. Aksamit
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Patent number: 6480032Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.Type: GrantFiled: March 4, 1999Date of Patent: November 12, 2002Assignee: Intel CorporationInventor: Randy J. Aksamit
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Patent number: 6462583Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.Type: GrantFiled: July 24, 2001Date of Patent: October 8, 2002Assignee: Intle CorporationInventor: Randy J. Aksamit
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Publication number: 20010045846Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.Type: ApplicationFiled: July 24, 2001Publication date: November 29, 2001Inventor: Randy J. Aksamit