Abstract: The present invention is a translation system that translates a definition of a prototyped programmable device defined in a programmable device specification into a generic behavioral model of the device and into lists of logic blocks and connections for implementing the device as a non-programmable device in an application specific target technology. The lists and behavioral models are used to create command files that drive logic synthesis and network connection list processing operations to generate a generic list of logic and network connections. The generic list and commands are used to create device test vectors for testing the behavior of the model and the target device design. The target technology lists and command files are processed to reduce redundant logic and are mapped into logic blocks and connection lists in the target technology. The operation of the target technology design is simulated using the target logic blocks and connections and the test vectors.

Abstract: A frequency selective hearing protection device and method utilizes adaptive filtering to hinder transmission of frequency components in ambient sound above a preselected threshold level. Sound frequency components which are not above the threshold level, such as normal speech, are allowed to pass. Electrical analog signals produced by a transducer are converted to a stream of digital input signals. The digital input signals are applied to a digital filter such as an FIR filter implementing a time domain difference equation. As a result, digital output signals are produced which are reconverted to analog output signals and applied to an actuator to produce audible sound. To adjust the frequency response of the invention to suppress gain at frequency components above the threshold, windows of input and output data signals are first assembled. Respective frequency domain transforms such as fast Fourier transforms provide spectrums representative of frequency component amplitudes.

Abstract: A low cost application specific integrated circuit tester is provided. The tester contains a microprocessor and a test vector RAM bank that is equal in BIT width as the input output pin count of a device under test. The RAM bank holds all vector information for the pins of the device under test. The tester board contains a number of tester ASICs placed between the test vector RAM bank and the devices under test. The tester ASICs are configurable to control the direction of data lines and to compare the results from the device under test to the preloaded RAM data. The present ASIC tester also provides a comparison of the results from two devices under test.

Abstract: A method and device for adapting a VME card for use in a VXI system are disclosed. The device resides on a circuit board that is plugged between the VXI bus and the VME card. The device provides two or more sets of VXI configuration registers. Each region of addresses normally used by the VME card is assigned to one of the simulated VXI units, and the device modifies incoming VXI addresses directed to each region so that the VME card responds to the VXI address. The VXI units simulated by the device may include one message-based device and one register-based device, so that both capabilities are available to the VME card. The device buffers signals passing between the VME card and the VXI bus, generating delays and timing signals to produce proper operation of all system components. The device provides bidirectional communication between the VME card and the VXI bus, so that the VME card can be the VXI bus master.

Abstract: A high-speed universal scaler operates in real time, accepting as an input an N-bit binary data word which is to be scaled (multiplied) by a scale factor specified in units per bit. The input data word is divided into M-bit sections which are provided (together with a count value indicating the position of the M-bit section within the input data word and a scale indicator value specifying which of a plurality of programmed scale factors values is to be used) sequentially as scaling addresses specifying binary coded decimal scale data in a scale memory. The sequential outputs of the scale memory in response to the scaling addresses are summed. When the sequence of addresses has been completed and all of the sequential memory outputs have been summed, the resulting sum will be a scaled binary coded decimal value equivalent to the input data word.