Abstract: A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer.

Abstract: Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: A control mechanism is provided for controlling the operation of a memory device. The control mechanism is contained within the memory device, and includes a buffer that receives data stored in the memory device and transmits the data to an output of the memory device. A logic device is coupled to the buffer controls the flow of data through the buffer by generating an output enable signal. The control mechanism may also include a counter coupled to a memory array. The counter identifies a memory entry within the memory array. A logic device is coupled to the counter and controls the operation of the counter.

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels.

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels.

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes.

Abstract: Filtering logic coupled between the microprocessor and the host bus to decode illegal special cycles executed by the processor to prevent these cycles from appearing on the host bus, which would otherwise be misinterpreted by logic coupled to the host bus. In the preferred embodiment, a modularized computer system based primarily on the 80386 or i486 microprocessors by Intel is upgraded to the new P5 or Pentium processor, also by Intel. The host and I/O buses are not modified and operate at the same speed and data width as in the previous systems. A processor board is upgraded with the P5 processor and includes the filtering logic according to the present invention. The P5 processor includes 8 byte enable bits as compared to the 4 byte enable bits used by the microprocessors 80386 and i486. Two new special cycles supported by the P5 processor are not supported by the previous host bus and would cause erroneous operation if allowed to be executed on the host bus.

Abstract: A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes.

Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.