Patents by Inventor Randy Mann
Randy Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9761594Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.Type: GrantFiled: October 2, 2013Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Bingwu Liu, Randy Mann
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Patent number: 9564375Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.Type: GrantFiled: October 15, 2013Date of Patent: February 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Randy Mann, Sandeep Puri, Sonia Ghosh, Anuj Gupta, Xusheng Wu
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Patent number: 9484300Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: GrantFiled: November 30, 2015Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sonia Ghosh, Randy Mann, Norman Chen, Shaowen Gao
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Publication number: 20160093565Abstract: Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: ApplicationFiled: November 30, 2015Publication date: March 31, 2016Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
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Patent number: 9263349Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: GrantFiled: November 8, 2013Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sonia Ghosh, Randy Mann, Norman Chen, Shaowen Gao
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Publication number: 20150130026Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Sonia GHOSH, Randy MANN, Norman CHEN, Shaowen GAO
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Publication number: 20150102826Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Randy MANN, Sandeep PURI, Sonia GHOSH, Anuj GUPTA, Xusheng WU
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Publication number: 20150091097Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Xusheng Wu, Bingwu Liu, Randy Mann
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Publication number: 20130001741Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Randy Mann, Kingsuk Maitra, Anurag Mittal
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Patent number: 7679083Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.Type: GrantFiled: March 30, 2007Date of Patent: March 16, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Min Chul Sun, Scott Jansen, Randy Mann, Oliver D. Patterson
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Publication number: 20080237586Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Min Chul Sun, Scott Jansen, Randy Mann, Oliver D. Patterson
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Publication number: 20080089116Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.Type: ApplicationFiled: December 3, 2007Publication date: April 17, 2008Inventors: Wayne Ellis, Randy Mann, David Wager, Robert Wong
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Publication number: 20070164337Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: March 16, 2007Publication date: July 19, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Charles Black, Alfred Grill, Randy Mann, Deborah Neumayer, Wilbur Pricer, Katherine Saenger, Thomas Shaw
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Publication number: 20070128776Abstract: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 ?.Type: ApplicationFiled: February 1, 2007Publication date: June 7, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Breitwisch, Chung Lam, Randy Mann, Dale Martin
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Publication number: 20070121370Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.Type: ApplicationFiled: November 29, 2005Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wayne Ellis, Randy Mann, David Wager, Robert Wong
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Publication number: 20060124982Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.Type: ApplicationFiled: December 15, 2004Publication date: June 15, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert Ho, John Barth, Ramachandra Divakaruni, Wayne Ellis, Johnathan Faltermeier, Brent Anderson, Subramanian Iyer, Deok-Kee Kim, Randy Mann, Paul Parries
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Publication number: 20060049443Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.Type: ApplicationFiled: October 31, 2005Publication date: March 9, 2006Applicant: International Business Machines CorporationInventors: James Adkisson, Charles Black, Alfred Grill, Randy Mann, Deborah Neumayer, Wilbur Pricer, Katherine Saenger, Thomas Shaw
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Publication number: 20060027889Abstract: The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 ?.Type: ApplicationFiled: August 5, 2004Publication date: February 9, 2006Applicant: International Business Machines CorporationInventors: Matthew Breitwisch, Chung Lam, Randy Mann, Dale Martin
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Publication number: 20060017066Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: ApplicationFiled: September 21, 2005Publication date: January 26, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Geiss, Marwan Khater, Qizhi Liu, Randy Mann, Robert Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas Stricker
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Publication number: 20050199908Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: ApplicationFiled: March 13, 2004Publication date: September 15, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Geiss, Marwan Khater, Qizhi Liu, Randy Mann, Robert Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas Stricker