Abstract: A modular multimedia platform includes a chassis into which a variety of modular input/output units, referred to as ports, may be inserted. The units may acquire an input signal and convert it to high precision digital information, or convert a digital signal to an analog signal and output the analog signal (or digital output may be provided). Multiple chassis can be connected together to increase the number of ports. A tag unit may be attached to any device coupled to a port. Each tag has a unique identification number to uniquely identify the device to which it is attached.

Abstract: A modular multimedia platform includes a chassis into which a variety of modular input/output units, referred to as ports, may be inserted. The units may acquire an input signal and convert it to high precision digital information, or convert a digital signal to an analog signal and output the analog signal (or digital output may be provided). Multiple chassis can be connected together to increase the number of ports. A tag unit may be attached to any device coupled to a port. Each tag has a unique identification number to uniquely identify the device to which it is attached.

Abstract: A modular multimedia platform includes a chassis into which a variety of modular input/output units, referred to as ports, may be inserted. The units may acquire an input signal and convert it to high precision digital information, or convert a digital signal to an analog signal and output the analog signal (or digital output may be provided). Multiple chassis can be connected together to increase the number of ports. A tag unit may be attached to any device coupled to a port. Each tag has a unique identification number to uniquely identify the device to which it is attached.

Abstract: An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid.

Abstract: A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals.

Abstract: Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.