Abstract: A safety sheet cargo tie-down system comprises a substantially rectangular safety sheet, and four securing straps which are fixedly secured to corner regions of the substantially rectangular safety sheet upon the forwardly disposed surface thereof. The securing straps are effectively brought around such corner regions to the rearwardly disposed surface so as to form a pair of securing straps arranged within a criss-crossed X-shaped array or arrangement. Each pair of securing straps has a slip-type fastener fixedly secured upon one free end portion of one of the securing straps, and the free end portion of the other one of the securing straps is passed through such fastener. In this manner, as each pair of securing straps is tightened, the safety sheet is properly secured with respect to cargo load barrels or drums.

Abstract: A method and system for effectuating network routing over primary and backup channels. In one embodiment, a primary link is enabled to transfer customer traffic between network nodes, while a transmission quality of the link is monitored. Upon determining the primary link has entered a marginal state, the primary link is disabled such that the network immediately determines it is unavailable. Test traffic is sent over the primary link while monitoring the transmission quality to determine if the link returns to a non-marginal state, and in response thereto the primary link is re-enabled such that the network immediately determines it is available for routing customer traffic again. In one embodiment, rerouting the customer traffic is effectuated by opening and closing the primary link, such that it appears to the network to be disconnected and reconnected. In one embodiment, the primary link comprises a free space optical (FSO) link.

Abstract: The entire right, title and interest in and to this application and all subject matter disclosed and/or claimed therein, including any and all divisions, continuations, reissues, etc., thereof are, effective as of the date of execution of this application, assigned, transferred, sold and set over by the applicant(s) named herein to Deere & Company, a Delaware corporation having offices at Moline, Ill. 61265, U.S.A., together with all rights to file, and to claim priorities in connection with, corresponding patent applications in any and all foreign countries in the name of Deere & Company or otherwise.

Abstract: An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A treadmill is provided that has a treadmill drive motor carriage that can pivot relative to a frame of the treadmill such that the incline of the treadmill can be controlled while the carriage can be moved to a position that permits upright storage of the treadmill on the carriage. This arrangement advantageously permits a walk through treadmill design to be used that can be stored uprightly. The treadmill can be equipped with a console and stanchion that can be folded against the deck of the treadmill. One incline arrangement pivots the carriage using an incline drive carried by the carriage that engages a gear grounded to the treadmill frame. Another preferred incline arrangement uses a four bar linkage movable carried by the frame that is driven by a linear actuator to pivot the carriage.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A method of forming a liner (and resultant structure) in a contact includes depositing a first layer of refractory metal, annealing the first layer, and sputter depositing a second layer of refractory metal or a compound or an alloy thereof, over the first layer.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: A semiconductor structure, and associated method of fabrication, comprising a substrate having a continuous buried oxide layer and having a plurality of trench isolation structures. The buried oxide layer may be located at more than one depth within the substrate. The geometry of the trench isolation structure may vary with depth. The trench isolation structure may touch or not touch the buried oxide layer. Two trench isolation structures may penetrate the substrate to the same depth or to different depths. The trench isolation structures provide insulative separation between regions within the substrate and the separated regions may contain semiconductor devices. The semiconductor structure facilitates the providing of digital and analog devices on a common wafer. A dual-depth buried oxide layer facilitates an asymmetric semiconductor structure.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: An object oriented computer apparatus and method provides a graphical user interface (GUI) for existing host-based (i.e., green screen) applications by defining some object oriented classes that reside on the client workstation, and by substituting function calls for display data in the green screen application with function calls that interface with the object oriented GUI defined by the classes. In this manner the present invention takes advantage of the processing power of client workstations in a network computing environment by having the client run the GUI. The underlying green screen application is modified to replace all display function calls with new function calls to the GUI, but this change is relatively minor and does not affect the underlying core logic of the application. In addition, the new function calls access the GUI screens directly without having to determine which screen is being displayed.

Abstract: A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

Abstract: The present invention provides an ablatively photodecomposable polymer having a photoabsorber bound to the polymer (the "ablatively photodecomposable polymer") which does not phase separate, nor does it crystallize. The ablatively photodecomposable polymer provides even ablation, high resolution and in preferred embodiments, can withstand potassium permanganate etchant and ferric chloride etchant. The ablatively photodecomposable polymer is strippable, although it can remain on the substrate if desired. The ablatively photodecomposable polymer comprises a polymer to which a photoabsorber is bound, either covalently or ionically. The present invention is also directed to a process for forming a metal pattern on a substrate employing the ablatively photodecomposable polymer.