Patents by Inventor Ranjan Rajoo
Ranjan Rajoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238336Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
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Patent number: 11658128Abstract: The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.Type: GrantFiled: August 19, 2021Date of Patent: May 23, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ranjan Rajoo, Venkata Narayana Rao Vanukuru
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Patent number: 11652069Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: GrantFiled: December 8, 2020Date of Patent: May 16, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ranjan Rajoo, Frank G. Kuechenmeister, Dirk Breuer
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Publication number: 20230056509Abstract: The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: RANJAN RAJOO, VENKATA NARAYANA RAO VANUKURU
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Patent number: 11444045Abstract: A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.Type: GrantFiled: August 16, 2020Date of Patent: September 13, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Ramasamy Chockalingam, Juan Boon Tan, Xiaodong Li, Kai Chong Chan, Ranjan Rajoo
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Publication number: 20220181271Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Ranjan RAJOO, Frank G. KUECHENMEISTER, Dirk BREUER
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Publication number: 20220052000Abstract: A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.Type: ApplicationFiled: August 16, 2020Publication date: February 17, 2022Inventors: RAMASAMY CHOCKALINGAM, JUAN BOON TAN, XIAODONG LI, KAI CHONG CHAN, RANJAN RAJOO
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Patent number: 11244915Abstract: A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.Type: GrantFiled: October 31, 2019Date of Patent: February 8, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ramasamy Chockalingam, Juan Boon Tan, Chee Kong Leong, Ranjan Rajoo, Xuesong Rao, Xiaodong Li
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Publication number: 20210134742Abstract: A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: RAMASAMY CHOCKALINGAM, JUAN BOON TAN, CHEE KONG LEONG, RANJAN RAJOO, XUESONG RAO, XIAODONG LI
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Patent number: 9768089Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.Type: GrantFiled: August 1, 2016Date of Patent: September 19, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ranjan Rajoo, Kai Chong Chan
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Patent number: 9761561Abstract: Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.Type: GrantFiled: March 18, 2015Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ranjan Rajoo, Kai Chong Chan
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Publication number: 20160343629Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Ranjan RAJOO, Kai Chong CHAN
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Publication number: 20160276310Abstract: Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.Type: ApplicationFiled: March 18, 2015Publication date: September 22, 2016Inventors: Ranjan RAJOO, Kai Chong CHAN
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Patent number: 9406577Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.Type: GrantFiled: March 10, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ranjan Rajoo, Kai Chong Chan
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Publication number: 20140264762Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.Type: ApplicationFiled: March 10, 2014Publication date: September 18, 2014Applicant: GLOBAL FOUNDRIES Singapore Pte. Ltd.Inventors: Ranjan RAJOO, Kai Chong CHAN
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Publication number: 20130328209Abstract: In an embodiment, a stack arrangement is provided. The stack arrangement may include a semiconductor arrangement, the semiconductor arrangement including a substrate; a via formed through the substrate; and a conductive portion arranged in the via. The stack arrangement may further include an interconnect portion arranged over the via; a bond pad portion arranged between the semiconductor arrangement and the interconnect portion, the bond pad portion may include a bond pad circumferential portion arranged at least partially circumferential with respect to the via and at a first distance away from the conductive portion; and at least one bond pad electrical connection extending from within the bond pad circumferential portion to the conductive portion; wherein the interconnect portion may be arranged away from the conductive portion via the bond pad portion.Type: ApplicationFiled: February 12, 2010Publication date: December 12, 2013Applicant: Agency for Science, Technology and ResearchInventors: Cheryl Sharmani Selvanayagam, Ranjan Rajoo, Xiaowu Zhang
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Publication number: 20090091025Abstract: A method for forming and releasing interconnects by using a dummy substrate. The method comprises applying metallization to the dummy substrate for creating a relatively strong bond between the metallization and the dummy substrate and a weak bond between a first end of each of the interconnects and the metallization; weakly bonding the first ends to the metallization; shaping the interconnects; releasing the weak bond between the metallization and the first ends by using a reduced release force to release the first end of the interconnects from the dummy substrate.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicant: Agency for Science, Technology and ResearchInventors: Ee Hua Wong, Ranjan Rajoo, Shoa Siong Lim
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Publication number: 20070256503Abstract: A bend testing apparatus for simulating free vibrational flexing at high speeds and frequencies in a test specimen, said apparatus comprising a cam having a narrow circumferential profile or linear profile wherein at least one portion of the profile of said cam comprises at least one waveform, a specimen holder that holds the test specimen on opposite ends of the test specimen in a default position, a light-weight deformation member operable to deflect at least one point on the test specimen from the default position, a follower with one end in operable contact with the cam and its other end connected to the deformation member, such that a displacement of the follower is according to the profile of the cam, to actuate the deformation member correspondingly and to deflect the at least one point on the test specimen from said default position upon movement of the cam.Type: ApplicationFiled: April 18, 2006Publication date: November 8, 2007Inventors: Ee Wong, Simon Seah, Ranjan Rajoo
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Publication number: 20070114266Abstract: A method and device to elongate a solder joint are provided. The method begins by forming an elongator on a first substrate. The elongator comprises an expander and an encapsulant to encapsulate the expander. A solder joint is formed to connect the first substrate to a second substrate. Thereafter, the encapsulant is softened to release the expander from a compressed state to elongate the solder joint. The device to elongate a solder joint comprises a substrate having an elongator formed on it. The elongator includes an expander in a compressed state and an encapsulant to encapsulate the expander.Type: ApplicationFiled: January 16, 2007Publication date: May 24, 2007Inventors: Ee Wong, Ranjan Rajoo, Wai Wong, Mahadevan Iyer
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Patent number: 7178711Abstract: A method and device to elongate a solder joint are provided. The method begins by forming an elongator on a first substrate. The elongator comprises an expander and an encapsulant to encapsulate the expander. A solder joint is formed to connect the first substrate to a second substrate. Thereafter, the encapsulant is softened to release the expander from a compressed state to elongate the solder joint. The device to elongate a solder joint comprises a substrate having an elongator formed on it. The elongator includes an expander in a compressed state and an encapsulant to encapsulate the expander.Type: GrantFiled: September 17, 2003Date of Patent: February 20, 2007Assignees: Agency for Science, Technology and Research, National Univeristy of Singapore, Georgia Tech Research CorporationInventors: Ee Hua Wong, Ranjan Rajoo, Wai Kwan Wong, Mahadevan Krishna Iyer