Abstract: Methods for forming microlenses on a semiconductor substrate are provided. An inductively coupled plasma etch process using a process gas that includes a mixture of CF4 and CHF3 can be used to modify the lens shape of a plurality of microlens objects located on a semiconductor substrate to meet microlens specifications in terms of curvature, height, length, shape, and/or distance between adjacent microlens objects on the substrate. The inductively coupled plasma process can be performed in an inductively coupled plasma processing apparatus that includes a grounded Faraday shield to prevent any capacitive coupling during the plasma etching process to reduce sputtering of the microlens surface.

Abstract: Methods for forming microlenses on a semiconductor substrate are provided. An inductively coupled plasma etch process using a process gas that includes a mixture of CF4 and CHF3 can be used to modify the lens shape of a plurality of microlens objects located on a semiconductor substrate to meet microlens specifications in terms of curvature, height, length, shape, and/or distance between adjacent microlens objects on the substrate. The inductively coupled plasma process can be performed in an inductively coupled plasma processing apparatus that includes a grounded Faraday shield to prevent any capacitive coupling during the plasma etching process to reduce sputtering of the microlens surface.

Abstract: A method for removing organic material over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to an outer zone of the plasma processing chamber, wherein the outer zone surrounds the inner zone and the second gas has a carbon containing component, wherein a concentration of the carbon containing component of the second gas is greater than a concentration of the carbon containing component in the first gas. Plasmas are simultaneously generated from the first gas and second gas. Some or all of the organic material is removed using the generated plasmas.

Abstract: Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Abstract: Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical dehydroxylation operation, wherein the halogen compound may be NH4F or CCl4.

Abstract: Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.

Abstract: A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH3SiH3, increasing the flow of SiH4 and keeping the flow of H2O2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO2 skin.

Abstract: A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH3SiH3, increasing the flow of SiH4 and keeping the flow of H2O2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO2 skin.

Abstract: Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical hydroxilation operation, wherein the halogen compound may be NH.sub.4 F or CCl.sub.4.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer.

Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO.sub.2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH.sub.3 SiH.sub.3, increasing the flow of SiH.sub.4 and keeping the flow of H.sub.2 O.sub.2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO.sub.2 skin.