Abstract: An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering.

Abstract: An electronic module comprising a multiplicity of prestacked IC chips, such as memory chips, and an IC chip, referred to as an active substrate or active backplane, to which the stack of chips is directly secured. A multiplicity of aligned solder bumps may interconnect the stack and the substrate, providing electrical, mechanical and thermal interconnection. The active substrate is a layer containing substantial amounts of integrated circuitry, which interfaces, on one hand, with the integrated circuitry in the stacked chips, and, on the other hand, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.

Abstract: This disclosure describes a system for providing a communications channel between a master computer and a plurality of similar or dissimilar slave computers that may be separated by great distances. The foregoing system comprises a buffer unit and at least one computer linkage unit. The buffer unit acts as an interface between the master or control computer, the external hardware that is coupled to the master computer and a plurality of slave computers, and the one or more computer linkage units so that the buffer unit may act as an expandable direct memory access bus to a slave computer and provide communication with a plurality of peripheral systems. The computer linkage unit performs all of the remaining interface functions between the master computer and the plurality of slave computers that are coupled to the master computer.