Patents by Inventor Rashed Ahmed

Rashed Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942871
    Abstract: A system includes a transformer, a first controller, a discharge circuit to discharge an external capacitor based on an undervoltage threshold, and a second controller. The second controller is coupled to the discharge circuit, and is also coupled to receive a rectified Ac voltage and to receive control signals from the first controller. The second controller includes a gate driver to turn on a primary field effect transistor (FET). The second controller also includes a startup controller coupled to the gate driver. The startup controller is configured to increase a duty cycle of the primary FET based on whether a control signal is received from the first controller. The startup controller is also configured to determine a current duty cycle of the primary FET and to turn off the primary FET based on whether the voltage of the AC-DC converter is above an undervoltage threshold.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 26, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Pavan Kumar Kuchipudi, Myeongseok Lee, Murtuza Lilamwala
  • Patent number: 11418108
    Abstract: A system includes a transformer having a primary winding and an auxiliary winding at a primary side of an AC-DC converter, the auxiliary winding reflecting an output voltage of a secondary winding of the transformer. A primary side controller includes an over-voltage protection (OVP) pin and an OVP circuit. A voltage divider includes a first resistor coupled between the auxiliary winding and the OVP pin and a second resistor coupled between the first resistor and a ground. The voltage divider provides, to OVP pin, a reduced voltage that is proportional to the output voltage. In absence of a pulse signal from a secondary side controller, the OVP circuit turns off a gate driver that drives a primary switch in response to the OVP voltage exceeding a reference OVP voltage. The primary switch is coupled between the primary winding of the transformer and the ground.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 16, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Murtuza Lilamwala
  • Publication number: 20220200476
    Abstract: A system includes a transformer, a first controller, a discharge circuit to discharge an external capacitor based on an undervoltage threshold, and a second controller. The second controller is coupled to the discharge circuit, and is also coupled to receive a rectified Ac voltage and to receive control signals from the first controller. The second controller includes a gate driver to turn on a primary field effect transistor (FET). The second controller also includes a startup controller coupled to the gate driver. The startup controller is configured to increase a duty cycle of the primary FET based on whether a control signal is received from the first controller. The startup controller is also configured to determine a current duty cycle of the primary FET and to turn off the primary FET based on whether the voltage of the AC-DC converter is above an undervoltage threshold.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Pavan Kumar Kuchipudi, Myeongseok Lee, Murtuza Lilamwala
  • Publication number: 20220200438
    Abstract: A system includes a transformer having a primary winding and an auxiliary winding at a primary side of an AC-DC converter, the auxiliary winding reflecting an output voltage of a secondary winding of the transformer. A primary side controller includes an over-voltage protection (OVP) pin and an OVP circuit. A voltage divider includes a first resistor coupled between the auxiliary winding and the OVP pin and a second resistor coupled between the first resistor and a ground. The voltage divider provides, to OVP pin, a reduced voltage that is proportional to the output voltage. In absence of a pulse signal from a secondary side controller, the OVP circuit turns off a gate driver that drives a primary switch in response to the OVP voltage exceeding a reference OVP voltage. The primary switch is coupled between the primary winding of the transformer and the ground.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Murtuza Lilamwala
  • Patent number: 11114945
    Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Hariom Rai
  • Patent number: 11018595
    Abstract: A secondary controlled AC-DC converter including an oscillator in a primary-side controller (PSC), and method for operating the same to enable soft-start and low frequency operation are provided. Generally, the method includes driving a power switch coupled between an AC input and a primary-side of the converter with a gate-drive (GD-signal). At startup and following auto-restart the GD-signal is generated using an oscillator-signal from the oscillator. After receiving start-stop pulses from a secondary-side controller, the oscillator-signal is decoupled from the GD-signal using a controller in the PSC, and the PSC begins generating the GD-signal using pulse-width-modulated (PWM) generated using the start-stop pulses. The oscillator operates at a first frequency independent of the PWM signal. The PWM signal includes one of a number of frequencies selected based on a power drawn from the converter, and, in low power applications can be less than the first frequency.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 25, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pavan Kumar Kuchipudi, Myeongseok Lee, Rashed Ahmed, Murtuza Lilamwala
  • Publication number: 20210058000
    Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
    Type: Application
    Filed: September 25, 2019
    Publication date: February 25, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Hariom Rai