Patents by Inventor Rashmi Jha
Rashmi Jha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10944053Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: GrantFiled: March 28, 2019Date of Patent: March 9, 2021Assignee: UNIVERSITY OF CINCINNATIInventors: Rashmi Jha, Andrew Rush, Eric Herrmann
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Patent number: 10854812Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: GrantFiled: December 24, 2019Date of Patent: December 1, 2020Assignee: University of CincinnatiInventors: Rashmi Jha, Andrew Rush, Eric Herrmann
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Publication number: 20200144499Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: ApplicationFiled: December 24, 2019Publication date: May 7, 2020Applicant: University of CincinnatiInventors: Rashmi Jha, Andrew Rush, Eric Herrmann
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Patent number: 10553793Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: GrantFiled: March 28, 2019Date of Patent: February 4, 2020Assignee: University of CincinnatiInventors: Rashmi Jha, Andrew Rush, Eric Herrmann
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Publication number: 20190305046Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: ApplicationFiled: March 28, 2019Publication date: October 3, 2019Applicant: University of CincinnatiInventors: Rashmi Jha, Andrew Rush, Eric Herrmann
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Publication number: 20190305220Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.Type: ApplicationFiled: March 28, 2019Publication date: October 3, 2019Applicant: University of CincinnatiInventors: RASHMI JHA, Andrew Rush, Eric Herrmann
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Patent number: 9564505Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: GrantFiled: April 17, 2014Date of Patent: February 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Publication number: 20140225199Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: ApplicationFiled: April 17, 2014Publication date: August 14, 2014Applicant: International Business Machines CorporationInventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Patent number: 8753936Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: GrantFiled: August 12, 2008Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Patent number: 8502343Abstract: A nanoelectric memristor device includes a first electrode and a layer of oxygen-vacancy-rich metal oxide deposited upon a surface of the first electrode. A layer of oxygen-rich/stochiometric metal oxide is deposited upon a surface of the oxygen-vacancy-rich metal oxide layer that is opposite from said first electrode. At least one of the oxygen-vacancy-rich metal oxide and oxygen-rich/stochiometric metal oxide layers is doped with one of a magnetic and a paramagnetic material. A second electrode is adjacent to a surface of the oxygen-rich/stochiometric metal oxide layer that is opposite from the oxygen-rich/stochiometric metal oxide layer.Type: GrantFiled: November 17, 2011Date of Patent: August 6, 2013Assignee: The University of ToledoInventors: Rashmi Jha, Jorhan Ordosgoitti, Branden Long
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Patent number: 8436427Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.Type: GrantFiled: April 6, 2011Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran, Richard S. Wise
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Patent number: 8183642Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: GrantFiled: February 2, 2011Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P Chudzik, Rashmi Jha, Siddarth A Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 8138041Abstract: Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.Type: GrantFiled: June 12, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Troy Graves-Abe, Rashmi Jha, Renee T. Mo, Keith Kwong Hon Wong
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Patent number: 8120144Abstract: Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.Type: GrantFiled: February 1, 2011Date of Patent: February 21, 2012Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Michael P. Chudzik, Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang
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Patent number: 8053306Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.Type: GrantFiled: December 13, 2007Date of Patent: November 8, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Rick Carter, Michael P. Chudzik, Rashmi Jha, Naim Moumen
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Publication number: 20110180880Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran, Richard S. Wise
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Patent number: 7955926Abstract: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.Type: GrantFiled: March 26, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Wesley C. Natzle, Renee T. Mo, Rashmi Jha, Kathryn T. Schonenberg, Richard A. Conti
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Publication number: 20110121436Abstract: Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.Type: ApplicationFiled: February 1, 2011Publication date: May 26, 2011Inventors: Michael P. Chudzik, Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang
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Publication number: 20110121401Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: ApplicationFiled: February 2, 2011Publication date: May 26, 2011Applicant: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Rashmi Jha, Siddarth A. Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri
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Patent number: 7947549Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.Type: GrantFiled: February 26, 2008Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P Chudzik, Rashmi Jha, Siddarth A Krishnan, Naim Moumen, Vijay Narayanan, Vamsi Paruchuri