Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Abstract: Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.

Abstract: Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.

Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Abstract: Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.

Abstract: An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.

Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.

Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.

Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.

Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.