Patents by Inventor Raul-Adrian Cernea
Raul-Adrian Cernea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200098779Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.Type: ApplicationFiled: September 20, 2019Publication date: March 26, 2020Applicant: SUNRISE MEMORY CORPORATIONInventors: Raul Adrian Cernea, Wu-Yi Henry Chien, Eli Harari
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Publication number: 20200051990Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.Type: ApplicationFiled: July 11, 2019Publication date: February 13, 2020Applicant: Sunrise Memory CorporationInventors: Eli Harari, Raul Adrian Cernea, George Samachisa, Wu-Yi Henry Chien
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Publication number: 20190156900Abstract: Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.Type: ApplicationFiled: November 16, 2018Publication date: May 23, 2019Applicant: Sunrise Memory CorporationInventor: Raul Adrian Cernea
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Patent number: 10204679Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.Type: GrantFiled: November 10, 2016Date of Patent: February 12, 2019Assignee: INNOVATIVE MEMORY SYSTEMS, INC.Inventor: Raul-Adrian Cernea
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Publication number: 20180366485Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.Type: ApplicationFiled: June 12, 2018Publication date: December 20, 2018Applicant: Sunrise Memory CorporationInventors: Eli Harari, Raul Adrian Cernea
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Patent number: 10037810Abstract: The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.Type: GrantFiled: June 27, 2017Date of Patent: July 31, 2018Assignee: SanDisk Technologies LLCInventors: Hemant Shukla, Saurabh Kumar Singh, Sridhar Yadala, Raul-Adrian Cernea, Anirudh Amarnath
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Patent number: 9946468Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.Type: GrantFiled: March 15, 2017Date of Patent: April 17, 2018Assignee: SanDisk Technologies LLCInventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
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Patent number: 9881676Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.Type: GrantFiled: October 11, 2016Date of Patent: January 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jong Hak Yuh, Raul Adrian Cernea, Seungpil Lee, Yen-Lung Jason Li, Qui Nguyen, Tai-Yuan Tseng, Cynthia Hsu
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Patent number: 9825048Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.Type: GrantFiled: August 13, 2015Date of Patent: November 21, 2017Assignee: SanDisk Technologies LLCInventor: Raul Adrian Cernea
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Publication number: 20170185299Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.Type: ApplicationFiled: March 15, 2017Publication date: June 29, 2017Applicant: SanDisk Technologies LLCInventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
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Publication number: 20170125088Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.Type: ApplicationFiled: November 10, 2016Publication date: May 4, 2017Inventor: Raul-Adrian Cernea
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Patent number: 9640253Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.Type: GrantFiled: July 7, 2016Date of Patent: May 2, 2017Assignee: SanDisk Technologies LLCInventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
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Patent number: 9595317Abstract: A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.Type: GrantFiled: October 30, 2015Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Yen-Lung Li, Raul-Adrian Cernea, Jong Hak Yuh, Tai-Yuan Tseng
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Publication number: 20170047339Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.Type: ApplicationFiled: August 13, 2015Publication date: February 16, 2017Inventor: Raul Adrian Cernea
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Publication number: 20170040381Abstract: A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: Yung-Tin Chen, Steven J. Radigan, Roy E. Scheuerlein, Raul Adrian Cernea
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Publication number: 20160351254Abstract: A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.Type: ApplicationFiled: October 30, 2015Publication date: December 1, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yen-Lung Li, Raul-Adrian Cernea, Jong Hak Yuh, Tai-Yuan Tseng
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Patent number: 9496272Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.Type: GrantFiled: September 24, 2014Date of Patent: November 15, 2016Assignee: SanDisk Technologies LLCInventor: Raul Adrian Cernea
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Publication number: 20160314834Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.Type: ApplicationFiled: July 7, 2016Publication date: October 27, 2016Applicant: SanDisk Technologies LLCInventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
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Patent number: 9478557Abstract: A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. This structure allows reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. In particular, with only three masks, the even memory cells are fabricated to have their word line socket component enlarged to overlap with those of the odd memory cells in order to form continuous word lines in the row direction.Type: GrantFiled: August 13, 2015Date of Patent: October 25, 2016Assignee: SanDisk Technologies LLCInventor: Raul Adrian Cernea
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Patent number: 9431411Abstract: A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. This structure allows reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. In particular, with only three masks, the even memory cells are fabricated to have their word line socket component enlarged to overlap with those of the odd memory cells in order to form continuous word lines in the row direction.Type: GrantFiled: August 13, 2015Date of Patent: August 30, 2016Assignee: SanDisk Technologies LLCInventor: Raul Adrian Cernea