Patents by Inventor Raul Esteban Silvera

Raul Esteban Silvera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7487497
    Abstract: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Zhixing Ren, Raul Esteban Silvera, Guansong Zhang
  • Patent number: 7472382
    Abstract: Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: Roch Georges Archambault, Shimin Cui, Raul Esteban Silvera
  • Publication number: 20080301656
    Abstract: A computer implemented method, apparatus, and computer program product for compiling source code. The source code is scanned to identify a candidate region. A procedure control descriptor is corresponding to the candidate region is generated. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false. Also responsive to the determination, code is further generated to correctly select one of the first region and the second region at runtime.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Inventors: Roch Georges Archambault, Shimin Cui, Yaoqing Gao, Raul Esteban Silvera, Peng Zhao
  • Patent number: 7228391
    Abstract: A system and method for lock caching for compound atomic operations (i.e. a read or write operation to more than one 4-byte word) on shared memory is provided. In a computer system including a memory shared among a plurality of processing entities, for example, multiple threads, a method of performing compound atomic operations comprises providing a pool of locks for synchronizing access to the memory; assigning the locks among the plurality of entities to minimize lock contention; and performing the compound atomic operations using the assigned locks. Each lock may be assigned in accordance with an address of the shared memory from the processing entity's compound atomic operations. Assigning locks may be performed in a manner to minimize concurrent atomic updates to the same or overlapping portions of the shared memory.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Raul Esteban Silvera, Robert James Blainey